公开(公告)号：US20240421591A1

公开(公告)日：2024-12-19

申请号：US18209361

申请日：2023-06-13

Applicant: Intel Corporation

Inventor： Harshit Dhakad ,  Yossi Shoshany ,  Sergey Sofer ,  Suhwan Kim ,  Krzysztof Domanski

IPC: H02H9/04 ,  H01L27/02 ,  H03K19/003

Abstract: Techniques and mechanisms for a DC-DC voltage converter to mitigate a risk of damage to circuitry due to electrostatic discharge (ESD). In an embodiment, a protection circuit of the DC-DC voltage converter comprises a pull-up circuit and a pull-down circuit which are coupled in series between a first interconnect and a second interconnect, which are to receive a first supply voltage and a second supply voltage, respectively. A voltage divider comprises capacitors which are coupled in series with each other between the first interconnect and the second interconnect. Control circuitry is coupled with the voltage divider, and is further coupled to automatically configure a first operational mode based on an ESD event. During the first mode, the pull-up circuit is disabled and the pull-down circuit is enabled. In another embodiment, a resistor-capacitor (RC) circuit automatically transitions the protection circuit from the first mode.