公开(公告)号：US20200226124A1

公开(公告)日：2020-07-16

申请号：US16832853

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Zeshan Chishti ,  Alaa Alameldeen ,  Abanti Basak

IPC: G06F16/23 ,  G06F16/901 ,  G06F16/2455

Abstract: Example methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement edge batch reordering for streaming graph analytics are disclosed. Example apparatus to provide reordered batches of edges to update a streaming graph include an edge clusterer to reorder, based on vertices of the streaming graph, a first batch of input edges to determine a first reordered batch of input edges. Disclosed example apparatus also include a graph update analyzer to compute a first performance metric associated with a first update operation performed on the streaming graph with the first reordered batch of input edges, and determine, based on at least the first performance metric, whether to reorder a second batch of input edges to be processed by a second update operation to be performed on the streaming graph.

公开(公告)号：US20250004775A1

公开(公告)日：2025-01-02

申请号：US18345909

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Zeshan Chishti ,  Jeffrey Cook ,  Thomas McDonald

IPC: G06F9/38

Abstract: Systems, methods, and apparatuses relating to hardware for auto-predication for loops with dynamically varying iteration counts are disclosed. In an embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to identify a plurality of popular iteration counts for a loop and to predicate a region including a number of loop iterations equal to one of the plurality of popular iteration counts.

公开(公告)号：US20190102314A1

公开(公告)日：2019-04-04

申请号：US15721572

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Zeshan Chishti ,  Nagi Aboulenein ,  Zvika Greenfield

IPC: G06F12/0895 ,  G06F12/0873 ,  H04W52/22 ,  H04W52/24

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a workload characteristic for a tag cache, and adjust a power parameter for the tag cache based on the workload characteristic. Other embodiments are disclosed and claimed.