公开(公告)号：US20230094171A1

公开(公告)日：2023-03-30

申请号：US17485370

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Avishay SNIR ,  Ziv CHAI ,  Siddhartha CHHABRA ,  Prashant DEWAN ,  Baiju PATEL

IPC: G06F12/14 ,  G06F12/02 ,  G06F12/0882

Abstract: Techniques for memory assisted inline encryption/decryption are described. An example includes an encryption data structure engine to provide a key, data, and a tweak to the encryption/decryption engine, wherein the encryption data structure engine is to: read an index value from an encryption data structure lookup data structure entry using an address, the entry to include the index value and a guest page physical address (GPPA), retrieve, based on the index value, an entry from the encryption data structure, the entry to include a logical block address (LBA) base, a key identifier, and at least one GPPA in a sequence of GPPAs, generate a LBA using a position of the GPPA from the encryption data structure lookup data structure entry in the sequence of GPPAs, and retrieve a key based on the key identifier, wherein the encryption engine to encrypt data using the retrieved key, and the generated LBA.