INSTRUCTION AND LOGIC FOR EXECUTION CONTEXT GROUPS FOR PARALLEL PROCESSING
    1.
    发明申请
    INSTRUCTION AND LOGIC FOR EXECUTION CONTEXT GROUPS FOR PARALLEL PROCESSING 审中-公开
    执行并行处理语境组的指导和逻辑

    公开(公告)号:US20160378471A1

    公开(公告)日:2016-12-29

    申请号:US14750807

    申请日:2015-06-25

    CPC classification number: G06F9/3851 G06F9/4856 Y02D10/24 Y02D10/32

    Abstract: A processor includes cores and a context management circuit. The circuit includes logic to determine an execution context group (ECG) to be migrated between cores. The ECG is to include application threads. The circuit also includes logic to halt all execution contexts in the ECG before migrating the ECG, reassign processor affinity to designate the target core, and restart execution of the ECG.

    Abstract translation: 处理器包括核心和上下文管理电路。 该电路包括用于确定要在核之间迁移的执行上下文组(ECG)的逻辑。 心电图包括应用程序线程。 该电路还包括在迁移ECG之前停止ECG中的所有执行上下文的逻辑,重新分配处理器亲和度以指定目标核心,并重新启动ECG的执行。

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