公开(公告)号：US20180014268A1

公开(公告)日：2018-01-11

申请号：US15205023

申请日：2016-07-08

Applicant: Intel IP Corporation

Inventor： Vijaykumar KUPPUSAMY ,  Alexei DAVYDOV

IPC: H04W56/00 ,  H04L25/02 ,  H04B1/40

CPC classification number: H04W56/0035 ,  H04B1/40 ,  H04L25/0202 ,  H04L27/266

Abstract: A circuit arrangement includes a channel estimation circuit configured to acquire a channel estimate including a plurality of channel samples based on a range of time and frequency locations of a received signal, a first calculation circuit configured to calculate a first time and frequency correlation product of the channel estimate and a second calculation circuit configured to calculate a second time and frequency correlation product of the channel estimate, a time offset circuit configured to determine a time offset based on the first time and frequency correlation product and the second time and frequency correlation product, and a frequency offset circuit configured to determine a frequency offset based on the first time and frequency correlation product and the second time and frequency correlation product.