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公开(公告)号:US20240047341A1
公开(公告)日:2024-02-08
申请号:US17880359
申请日:2022-08-03
发明人: Ruilong Xie , Nicholas Anthony Lanzillo , Brent A. Anderson , Reinaldo Vega , Albert M. Chu , Lawrence A. Clevenger
IPC分类号: H01L23/522 , H01L23/528 , H01L21/768
CPC分类号: H01L23/5226 , H01L23/5283 , H01L21/76877 , H01L21/76816
摘要: Interconnect designs with reduced via resistance are provided. In one aspect, an interconnect structure includes: at least a first metal line and a second metal line; and a conductive via in between the first metal line and the second metal line, wherein the conductive via has elongated dimensions along a major axis of the first metal line and along a major axis of the second metal line. Dielectric caps can be present on the first metal lines, and below and above the second metal lines. A method of forming the present interconnect structure is also provided.