公开(公告)号：US10127121B2

公开(公告)日：2018-11-13

申请号：US15172248

申请日：2016-06-03

申请人： International Business Machines Corporation

发明人： Khandker N. Adeeb ,  Steven J. Battle ,  Brandon R. Goddard ,  Dung Q. Nguyen ,  Tu-An T. Nguyen ,  Nicholas R. Orzol ,  Brian D. Victor ,  Brendan M. Wong

IPC分类号： G06F11/00 ,  G06F11/14

摘要： Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where the load/store slices are coupled to the execution slices via a results bus. Operation of such a multi-slice processor includes: capturing first state information corresponding to a first set of control signals; monitoring state information of a plurality of logical components of the multi-slice processor; selecting, in dependence upon one or more selection criteria and upon the monitored state information, a second set of control signals; and capturing second state information corresponding to the second set of control signals, wherein the first set of control signals is different than the second set of control signals.

公开(公告)号：US10037259B2

公开(公告)日：2018-07-31

申请号：US15138593

申请日：2016-04-26

申请人： International Business Machines Corporation

发明人： Khandker N. Adeeb ,  Steven J. Battle ,  Brandon R. Goddard ,  Dung Q. Nguyen ,  Tu-An T. Nguyen ,  Nicholas R. Orzol ,  Brian D. Victor ,  Brendan M. Wong

IPC分类号： G06F11/00 ,  G06F11/34 ,  G06F11/30 ,  G01R31/317

CPC分类号： G06F11/3495 ,  G01R31/31705 ,  G06F11/3024

摘要： Systems, methods, and apparatuses to perform an operation comprising receiving an indication of a first error in a processor, identifying a first control signal, of a plurality of control signals in a debug bus, associated with the error, wherein each of the plurality of control signals are coupled to one of a plurality of input ports of a multiplexer, and changing a configuration state of the multiplexer to output the first control signal to a trace array.

公开(公告)号：US10318294B2

公开(公告)日：2019-06-11

申请号：US15186744

申请日：2016-06-20

申请人： International Business Machines Corporation

发明人： Khandker N. Adeeb ,  Joshua W. Bowman ,  Jeffrey C. Brownscheidle ,  Brandon R. Goddard ,  Dung Q. Nguyen ,  Tu-An T. Nguyen ,  Brian D. Victor ,  Brendan M. Wong

IPC分类号： G06F9/30

摘要： Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: receiving a first instruction indicating a first target register; receiving a second instruction indicating the first target register as a source operand; responsive to the second instruction indicating the first target register as a source operand, updating a dependent count corresponding to the first instruction; and issuing, in dependence upon the dependent count for the first instruction being greater than a dependent count for another instruction, the first instruction to an execution slice of the plurality of execution slices.