HARDWARE-BASED TRACE ASSIST UNIT
    2.
    发明申请

    公开(公告)号:US20250036542A1

    公开(公告)日:2025-01-30

    申请号:US18361565

    申请日:2023-07-28

    Abstract: A trace assist unit operable with a plurality of processor cores is described. The trace assist unit comprises a plurality of physical buffers, and loading circuitry and unloading circuitry that are communicatively coupled with the plurality of physical buffers. The loading circuitry receives trace events from various ones of the plurality of processor cores, each of the trace events having a respective category from a plurality of predefined categories. The loading circuitry writes the trace events to respective ones of the plurality of physical buffers that are assigned to the respective categories of the plurality of predefined categories. The loading circuitry transmits, responsive to one or more predefined conditions, an unload signal to the unloading circuitry to unload contents of a selected physical buffer of the plurality of physical buffers to an external memory.

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