SYSTEM AND METHOD FOR QUANTUM CIRCUIT DESIGN FOR COGNITIVE INTERFERENCE EFFECTS

    公开(公告)号:US20240095570A1

    公开(公告)日:2024-03-21

    申请号:US18469104

    申请日:2023-09-18

    Applicant: IonQ, Inc.

    CPC classification number: G06N10/40 G06N10/20 G06N10/60

    Abstract: A system and method is provided for designing and configuring a quantum circuit that models known “interference effects” between mutually exclusive events whose outcome is not yet known. An exemplary method includes applying a laser to an ion trap to set a probability of a single event by rotating at least one qubit; configuring the quantum circuit to connect a plurality of events, such that an outcome of the single event dictates an output of a subsequent event to be more or less likely to occur; configuring the quantum circuit to entangle the respective plurality of events such that a plurality of states representing different potential events interfere with one another, including an interference between incompatible outcomes of at least two of the plurality of events; and configuring the quantum circuit to measures the respective outcomes to model a result when the quantum computer determines an outcome of an event, such that possible outcomes of other events are removed.

    Addition of Qubit States Using Entangled Quaternionic Roots of Single-Qubit Gates

    公开(公告)号:US20240169241A1

    公开(公告)日:2024-05-23

    申请号:US18175946

    申请日:2023-02-28

    Applicant: IonQ, Inc.

    CPC classification number: G06N10/40 G06F7/5525 G06N10/20

    Abstract: Systems and methods are provided for performing addition of qubit states using entangled quaternionic roots of single qubit gates. A method includes identifying a single qubit gate in a quantum circuit of a quantum computer, wherein the quantum circuit includes two summand qubits entangled with a third qubit that stores a measurable non-linear sum of the two summand qubits. The method includes mapping the single qubit gate to a representative gate that is phase-equivalent to the single qubit gate, mapping the representative gate to a unit quaternion, calculating an nth root of the unit quaternion, and mapping the nth root of the unit quaternion to a unitary matrix that represents a fractional single qubit gate. The method includes configuring the quantum circuit to include at least one fractional single qubit gate representing the unitary matrix in place of the single qubit gate for performing the addition.

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