公开(公告)号：US20080219065A1

公开(公告)日：2008-09-11

申请号：US12123539

申请日：2008-05-20

申请人： JAE-JUN LEE ,  HOE-JU CHUNG

发明人： JAE-JUN LEE ,  HOE-JU CHUNG

IPC分类号： G11C7/00

CPC分类号： H03L7/0812

摘要： A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided. The DLL circuit includes a replica output driver delaying an internal clock signal by a first delay time to output a first internal clock signal, the first delay time is a delay time of the internal clock signal which is generated by an output driver when a first load of a first magnitude is connected to an output terminal of the output driver, and a transfer/delay circuit transferring the first delay internal clock signal to a phase detector as a second delay internal clock signal when the first load is connected to the output terminal, and outputting the second delay internal clock signal to the phase detector by delaying the first delay internal clock signal by a second delay time, the second delay time is a delay time of the internal clock signal which is generated by the output driver when a second load of a second magnitude, which is larger than the first magnitude, is connected to the output terminal.

摘要翻译： 用于同步半导体存储器件的延迟锁定环（DLL）电路，其可以根据外部负载的大小来控制DLL电路内的反馈回路的延迟时间，以及生成关于连接到数据的负载的信息的方法 提供同步半导体存储器件的引脚。 DLL电路包括复制输出驱动器，延迟第一延迟时间的内部时钟信号以输出第一内部时钟信号，第一延迟时间是当输出驱动器第一次加载时产生的内部时钟信号的延迟时间 第一幅度的第一延迟连接到输出驱动器的输出端，以及传输/延迟电路，当第一负载连接到输出端时，将第一延迟内部时钟信号传送到相位检测器作为第二延迟内部时钟信号， 并且通过将所述第一延迟内部时钟信号延迟第二延迟时间，将所述第二延迟内部时钟信号输出到所述相位检测器，所述第二延迟时间是由所述输出驱动器产生的内部时钟信号的延迟时间， 大于第一幅度的第二幅度连接到输出端。