公开(公告)号：US20130166882A1

公开(公告)日：2013-06-27

申请号：US13335872

申请日：2011-12-22

申请人： Jack Hilaire CHOQUETTE ,  Robert J. STOLL ,  Olivier GIROUX ,  Michael FETTERMAN ,  Shirish GADRE ,  Robert Steven GLANVILLE ,  Alexandre JOLY

发明人： Jack Hilaire CHOQUETTE ,  Robert J. STOLL ,  Olivier GIROUX ,  Michael FETTERMAN ,  Shirish GADRE ,  Robert Steven GLANVILLE ,  Alexandre JOLY

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/312

CPC分类号： G06F9/3851 ,  G06F9/382

摘要： Systems and methods for scheduling instructions without instruction decode. In one embodiment, a multi-core processor includes a scheduling unit in each core for scheduling instructions from two or more threads scheduled for execution on that particular core. As threads are scheduled for execution on the core, instructions from the threads are fetched into a buffer without being decoded. The scheduling unit includes a macro-scheduler unit for performing a priority sort of the two or more threads and a micro-scheduler arbiter for determining the highest order thread that is ready to execute. The macro-scheduler unit and the micro-scheduler arbiter use pre-decode data to implement the scheduling algorithm. The pre-decode data may be generated by decoding only a small portion of the instruction or received along with the instruction. Once the micro-scheduler arbiter has selected an instruction to dispatch to the execution unit, a decode unit fully decodes the instruction.

摘要翻译： 用于调度指令而不进行指令解码的系统和方法。 在一个实施例中，多核处理器包括每个核心中的调度单元，用于调度来自在该特定核心上执行的两个或更多个线程的指令。 由于线程被安排在核心上执行，所以来自线程的指令被取入到缓冲器中而不被解码。 调度单元包括用于执行两个或更多个线程的优先级排序的宏调度器单元和用于确定准备执行的最高阶线程的微调度器仲裁器。 宏调度器单元和微调度器仲裁器使用预解码数据来实现调度算法。 预解码数据可以仅通过解码指令的一小部分或与该指令一起被接收来产生。 一旦微调度器仲裁器选择了向执行单元发送的指令，则解码单元对该指令进行完全解码。