公开(公告)号：US06490712B1

公开(公告)日：2002-12-03

申请号：US09684159

申请日：2000-10-04

申请人： James Daniel Merchant ,  Gordon Carskadon ,  Brian P. Evans ,  Jeffery Scott Hunt ,  Anup Nayak ,  Andrew Wright

发明人： James Daniel Merchant ,  Gordon Carskadon ,  Brian P. Evans ,  Jeffery Scott Hunt ,  Anup Nayak ,  Andrew Wright

IPC分类号： G06F1750

CPC分类号： G06F17/5054

摘要： A method and system for automatically identifying configuration cell addresses in a schematic hierarchy is disclosed. In one embodiment of the present invention, a memory cell (e.g., a configuration bit) is identified in a schematic hierarchy. Next, this embodiment determines an address for the memory cell. Then, this embodiment determines a unique name for the memory cell. The name is comprised of a hierarchical logical name and a schematic path name. By traversing the schematic and using logical names, all addresses of configuration bits of a circuit design may be automatically determined. The process is repeated for each memory cell in the schematic. This embodiment stores the unique name of the configuration bit and the address of the configuration bit in a data structure.

摘要翻译： 公开了用于自动识别示意图层次结构中的配置单元地址的方法和系统。 在本发明的一个实施例中，以示意性层次来识别存储器单元（例如，配置位）。 接下来，本实施例确定存储单元的地址。 然后，本实施例确定存储单元的唯一名称。 该名称由分层逻辑名称和示意图路径名称组成。 通过遍历原理图并使用逻辑名称，可以自动确定电路设计的配置位的所有地址。 在原理图中为每个存储单元重复该过程。 该实施例将配置位的唯一名称和配置位的地址存储在数据结构中。

公开(公告)号：US06904436B1

公开(公告)日：2005-06-07

申请号：US09684160

申请日：2000-10-04

申请人： James Daniel Merchant ,  Gordon Carskadon ,  Brian P. Evans ,  Jeffery Scott Hunt ,  Anup Nayak ,  Andrew Wright

发明人： James Daniel Merchant ,  Gordon Carskadon ,  Brian P. Evans ,  Jeffery Scott Hunt ,  Anup Nayak ,  Andrew Wright

IPC分类号： G06F7/08 ,  G06F17/50

CPC分类号： G06F17/5054 ,  Y10S707/956 ,  Y10S707/99942

摘要： A method and system for automatically building a bit order data structure of configuration bits for a programmable logic device. One embodiment of the present invention first identifies a plurality of memory cells in a hierarchical schematic representation of the programmable device. Next, this embodiment determines a plurality of addresses corresponding to the plurality of memory cells. This embodiment next determines a plurality of logical names for the plurality of memory cells. Then, based on an order in which the plurality of addresses are to be loaded into the programmable logic device, this embodiment orders the plurality of logical names for the plurality of memory cells. Another embodiment first accesses a database comprising a plurality of logical names corresponding to a plurality of addresses. Then, this embodiment accesses a database specifying an order in which the plurality of addresses are to be loaded into the programmable logic device. Next, this embodiment orders the plurality of logical names based on the order specified in the database from the previous step.

摘要翻译： 一种用于自动构建可编程逻辑器件的配置位的位顺序数据结构的方法和系统。 本发明的一个实施例首先以可编程设备的分层示意图表示识别多个存储器单元。 接下来，本实施例确定与多个存储单元对应的多个地址。 该实施例接下来确定多个存储单元的多个逻辑名称。 然后，基于将多个地址加载到可编程逻辑器件中的顺序，本实施例对多个存储器单元定义多个逻辑名称。 另一个实施例首先访问包括与多个地址对应的多个逻辑名称的数据库。 然后，本实施例访问指定将多个地址加载到可编程逻辑器件中的顺序的数据库。 接下来，本实施例基于从前一步骤在数据库中指定的顺序来订购多个逻辑名称。