公开(公告)号：US07466922B2

公开(公告)日：2008-12-16

申请号：US11167410

申请日：2005-06-27

申请人： Jay J. Pierce ,  Darrel Kanagy ,  David Schneider ,  Christopher A. Zuhlke

发明人： Jay J. Pierce ,  Darrel Kanagy ,  David Schneider ,  Christopher A. Zuhlke

IPC分类号： H04B10/04 ,  H04B10/06

CPC分类号： H04B10/40

摘要： The invention relates to optoelectronic modules for generating and/or receiving optical signals for use in fiber-optic communication systems, such as optical transponders or transceivers, having a reconfigurable control and status (C&S) interface with a host device. The optoelectronic module includes an electrical multi-pin host connector having a plurality of pins for communicating a plurality of digital C&S signals between the host and the module, functional hardware responsive to the digital control signals and comprising sensing means for generating digital status signals, and processing means formed by an FPGA and a processor for processing the digital C&S signals. The FPGA is disposed in communications paths between the host connector on one side, and the functional hardware and the processor on the other side, and programmed for routing each of the discrete C&S signals between the C&S pins of the host connector and the processor, and between the C&S pins and the functional hardware, thereby providing reconfigurability of said routing by downloading a different set of FPGA instructions.

摘要翻译： 本发明涉及用于生成和/或接收用于光纤通信系统（例如光转发器或收发器）的光信号的光电子模块，其具有与主机设备的可重新配置的控制和状态（C＆S）接口。 光电子模块包括具有用于在主机和模块之间传送多个数字C＆S信号的多个引脚的电多针主机连接器，响应于数字控制信号的功能硬件，并且包括用于产生数字状态信号的感测装置，以及 处理装置由FPGA和用于处理数字C＆S信号的处理器形成。 FPGA设置在一侧的主机连接器与另一侧的功能硬件和处理器之间的通信路径中，并被编程用于在主机连接器的C＆S引脚和处理器之间路由每个分立的C＆S信号，以及 在C＆S引脚和功能硬件之间，从而通过下载不同的FPGA指令集来提供所述路由的可重新配置。