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    METHOD AND APPARATUS FOR REDUCING AREA AND COMPLEXITY OF INSTRUCTION WAKEUP LOGIC IN A MULTI-STRAND OUT-OF-ORDER PROCESSOR
    1.
    发明申请
    METHOD AND APPARATUS FOR REDUCING AREA AND COMPLEXITY OF INSTRUCTION WAKEUP LOGIC IN A MULTI-STRAND OUT-OF-ORDER PROCESSOR 有权
    用于减少区域的方法和装置以及指令唤醒逻辑的复杂性在多条件的无序处理器

    公开(公告)号：US20130339679A1

    公开(公告)日：2013-12-19

    申请号：US13524240

    申请日：2012-06-15

    申请人： Jayesh IYER ,  Nikolay Kosarev ,  Sergey Shishlov ,  Alexey Sivtsov ,  Alexander Butuzov ,  Boris A. Babayan ,  Vladimir Penkovski

    发明人： Jayesh IYER ,  Nikolay Kosarev ,  Sergey Shishlov ,  Alexey Sivtsov ,  Alexander Butuzov ,  Boris A. Babayan ,  Vladimir Penkovski

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30032 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857

    摘要： A computer system, a computer processor and a method executable on a computer processor involve placing each sequence of a plurality of sequences of computer instructions being scheduled for execution in the processor into a separate queue. The head instruction from each queue is stored into a first storage unit prior to determining whether the head instruction is ready for scheduling. For each instruction in the first storage unit that is determined to be ready, the instruction is moved from the first storage unit to a second storage unit. During a first processor cycle, each instruction in the first storage unit that is determined to be not ready is retained in the first storage unit, and the determining of whether the instruction is ready is repeated during the next processor cycle. Scheduling logic performs scheduling of instructions contained in the second storage unit.

    摘要翻译： 计算机系统，计算机处理器和可在计算机处理器上执行的方法包括将计划执行的计算机指令的多个序列的每个序列放置在处理器中以进入单独的队列。 在确定头部指令是否准备好进行调度之前，来自每个队列的头部指令被存储到第一存储单元中。 对于确定准备好的第一存储单元中的每个指令，指令从第一存储单元移动到第二存储单元。 在第一处理器周期期间，确定未准备好的第一存储单元中的每个指令被保留在第一存储单元中，并且在下一处理器周期期间重复确定指令是否就绪。 调度逻辑执行包含在第二存储单元中的指令的调度。