公开(公告)号：US06580292B2

公开(公告)日：2003-06-17

申请号：US09922420

申请日：2001-08-02

申请人： Jeffrey Alma West ,  Robert John Marshall ,  Alma Anderson ,  Dominicus M Roozeboom

发明人： Jeffrey Alma West ,  Robert John Marshall ,  Alma Anderson ,  Dominicus M Roozeboom

IPC分类号： H03K190175

CPC分类号： H03K19/018585

摘要： The invention implements a Positive Emitter Coupled Logic (PECL) output using CMOS transistors that approximate the Motorola ECL characteristics into standard PECL termination schemes. By creating a PECL output using a switchable current source the PECL output can be integrated into a Low Voltage Differential Signaling (LVDS) structure. The invention allows the user to switch between PECL and LVDS outputs via control logic by enabling the specific circuit elements for each signaling technology. With this invention, the combination of two drivers on one IC device gives system designers the flexibility to use the same circuitry in two separate signaling schemes. Thus, the designers can select to use one output characteristics or the other for their designs.

摘要翻译： 本发明使用CMOS晶体管实现了正发射极耦合逻辑（PECL）输出，其将摩托罗拉ECL特性近似为标准PECL端接方案。 通过使用可切换电流源创建PECL输出，PECL输出可以集成到低电压差分信号（LVDS）结构中。 本发明允许用户通过使每个信号技术的特定电路元件经由控制逻辑在PECL和LVDS输出之间切换。 利用本发明，一个IC器件上的两个驱动器的组合为系统设计人员提供了在两个单独的信令方案中使用相同电路的灵活性。 因此，设计师可以选择使用一种输出特性或另一种用于其设计。

公开(公告)号：US06703883B2

公开(公告)日：2004-03-09

申请号：US09823417

申请日：2001-03-29

申请人： Jeffrey Alma West ,  Harold Garth Hanson ,  David W Oehler

发明人： Jeffrey Alma West ,  Harold Garth Hanson ,  David W Oehler

IPC分类号： G06F104

CPC分类号： H03K5/003 ,  G06F1/04 ,  H03K5/125

摘要： The invention provides a clock sensor that can be operated at very low current and power. This sensor can also detect an input clock signal with a very small amplitude to detect the presence of clock inputs. According to one embodiment of the invention, a clock sensor comprises an input circuit configured to receive an input clock signal; a biasing circuit configured to receive the input clock signal and to provide biasing voltages; and a switching circuit configured to receive the biasing voltage and in response to the input clock signal, to provide a switching signal for switching an output circuit to generate an output clock signal. The input clock signal may have a small amplitude and the output clock signal has a full amplitude.

摘要翻译： 本发明提供了一种可以在非常低的电流和功率下工作的时钟传感器。 该传感器还可以以非常小的幅度检测输入时钟信号，以检测时钟输入的存在。 根据本发明的一个实施例，时钟传感器包括被配置为接收输入时钟信号的输入电路; 偏置电路，被配置为接收输入时钟信号并提供偏置电压; 以及开关电路，被配置为接收所述偏置电压并且响应于所述输入时钟信号，以提供用于切换输出电路以产生输出时钟信号的开关信号。 输入时钟信号可能具有较小的幅度，并且输出时钟信号具有全幅度。

公开(公告)号：US06683505B2

公开(公告)日：2004-01-27

申请号：US09939326

申请日：2001-08-24

申请人： Jeffrey Alma West

发明人： Jeffrey Alma West

IPC分类号： H03B2400

CPC分类号： H03K3/0322 ,  H03B5/24 ,  H03K3/354

摘要： The invention provides an improved high speed voltage controlled oscillator (VCO) buffer cell, with consistent output performance. According to one embodiment of the invention, the cell comprises a differential pair of transistors and a current mirror circuit. The differential pair has input terminals for receiving input signals and output terminals for providing differential voltage swing in response to the input signals. The current mirror circuit is operably coupled to the pair of transistors and is configured to receive a first external reference current and provide a mirrored current to an active one of the transistors. The differential voltage swing has a frequency which is determined based on the reference current. In a specific embodiment of the invention, the pair of transistors of the cell is bipolar transistors, and the current mirror circuit is composed of CMOS transistors.

摘要翻译： 本发明提供了一种改进的高速压控振荡器（VCO）缓冲单元，具有一致的输出性能。 根据本发明的一个实施例，电池包括差分对晶体管和电流镜电路。 差分对具有用于接收输入信号的输入端子和用于响应于输入信号提供差分电压摆幅的输出端子。 电流镜电路可操作地耦合到该对晶体管，并且被配置为接收第一外部参考电流并且向晶体管中的有源晶体管提供镜像电流。 差分电压摆幅具有基于参考电流确定的频率。 在本发明的一个具体实施例中，单元的一对晶体管是双极晶体管，并且电流镜电路由CMOS晶体管组成。