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1.发明申请Stop waiting for source operand when conditional instruction will not execute 审中-公开当条件指令不执行时，停止等待源操作数公开(公告)号：US20060200654A1
公开(公告)日：2006-09-07
申请号：US11073165
申请日：2005-03-04
IPC分类号： G06F9/44
CPC分类号： G06F9/3824 , G06F9/3001 , G06F9/30072
摘要： The delay of non-executing conditional instructions, that would otherwise be imposed while waiting for late operand data, is alleviated based on an early recognition that such instructions will not execute on the current pass through a pipeline processor. At an appropriate point prior to execution, a determination regarding the condition is made. If the condition is such that the instruction will not execute on this pass through the pipeline, the hold with regard to the conditional instruction may be terminated, that is to say skipped or stopped prior to completion of receiving all the associated operand data. Flow of the non-executing instruction through the pipeline, for example, need not wait for an earlier instruction to compute and write source operand data for use by the conditional instruction.
摘要翻译： 基于早期识别这种指令将不会在当前通过流水线处理器的过程中执行的情况下，缓解不执行条件指令的延迟，否则将等待后期操作数数据施加。 在执行之前的适当时刻，作出关于条件的确定。 如果条件使得指令不会在通过流水线的该通过上执行，关于条件指令的保持可以被终止，也就是说在完成接收所有相关联的操作数数据之前被跳过或停止。 例如，通过流水线的不执行指令的流程不需要等待较早的指令来计算和写入源操作数数据以供条件指令使用。
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公开(公告)号：US20070174592A1
公开(公告)日：2007-07-26
申请号：US11336357
申请日：2006-01-20
CPC分类号： G06F9/30072 , G06F9/30036 , G06F9/30094 , G06F9/3016 , G06F9/30167
摘要： Delays due to waiting for operands that will not be used by a select operand instruction, are alleviated based on an early recognition that such operand data is not required in order to complete the processing of the select operand instruction. At appropriate points prior to execution, determinations are made regarding a selection criterion or criteria specified by the select operand instruction, conditions that affect the selection criteria, and the availability of operands. A hold circuit uses the determinations to control the activation and release of a hold signal that controls processor pipeline stalls. A stall required to wait for operand data is skipped or a stall is terminated early, if the selected operand is available even though the other operand, that will not be used, is not available. A stall due to waiting for operands is maintained until the selection criteria is met and the selected operand is fetched and made available.
摘要翻译： 由于等待操作数不被选择操作数指令使用的延迟，基于早期识别，为了完成选择操作数指令的处理而不需要这种操作数数据，可以减轻延迟。 在执行之前的适当点，确定关于由选择操作数指令指定的选择标准或标准，影响选择标准的条件以及操作数的可用性。 保持电路使用该确定来控制控制处理器流水线停顿的保持信号的激活和释放。 如果所选择的操作数可用，即使不使用另一个操作数不可用，则跳过等待操作数数据所需的档位或提前终止档位。 维持由于等待操作数而导致的停顿，直到满足选择标准并且所选择的操作数被获取并可用。
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公开(公告)号：US20070038826A1
公开(公告)日：2007-02-15
申请号：US11201542
申请日：2005-08-10
CPC分类号： G06F9/30105 , G06F9/30141
摘要： A register file is disclosed. The register file includes a plurality of registers and a decoder. The decoder may be configured to receive an address for any one of the registers, and disable a read operation to the addressed register if data in the addressed register is invalid.
摘要翻译： 公开了一种寄存器文件。 寄存器文件包括多个寄存器和解码器。 解码器可以被配置为接收任何一个寄存器的地址，并且如果寻址的寄存器中的数据无效，则禁止对寻址的寄存器的读取操作。
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公开(公告)号：US20060174090A1
公开(公告)日：2006-08-03
申请号：US11050932
申请日：2005-02-03
申请人： Thomas Sartorius , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Rodney Smith
发明人： Thomas Sartorius , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Rodney Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.
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公开(公告)号：US20060236078A1
公开(公告)日：2006-10-19
申请号：US11106803
申请日：2005-04-14
申请人： Thomas Sartorius , James Dieffenderfer , Jeffrey Bridges , Kenneth Dockser , Michael McIlvaine , Rodney Smith
发明人： Thomas Sartorius , James Dieffenderfer , Jeffrey Bridges , Kenneth Dockser , Michael McIlvaine , Rodney Smith
IPC分类号： G06F9/44
CPC分类号： G06F9/30072 , G06F9/3826 , G06F9/3838 , G06F9/384
摘要： A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.
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6.发明申请Power saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor state 有权省电方法和装置，用于基于已知的处理器状态选择性地启用CAM重命名寄存器文件中的比较器公开(公告)号：US20060206688A1
公开(公告)日：2006-09-14
申请号：US11072849
申请日：2005-03-03
CPC分类号： G06F9/30058 , G06F1/3203 , G06F1/3275 , G06F9/384 , Y02D10/13 , Y02D10/14
摘要： A renaming register file complex for saving power is described. A mapping unit transforms an instruction register number (IRN) to a logical register number (LRN). The renaming register file maps an LRN to a physical register number (PRN), there being a greater number of physical registers than addressable by direct use of the IRN. The renaming register file uses a content addressable memory (CAM) to provide the mapping function. The renaming register file CAM further uses current processor state information to selectively enable tag comparators to minimize power in accessing registers. When a tag comparator is not enabled it remains in a low power state. A processor using a renaming register file with low power features is also described.
摘要翻译： 描述了一种用于节省电力的重命名寄存器文件。 映射单元将指令寄存器号（IRN）变换为逻辑寄存器号（LRN）。 重命名寄存器文件将LRN映射到物理寄存器编号（PRN），通过直接使用IRN，存在比可寻址的更大数量的物理寄存器。 重命名寄存器文件使用内容可寻址存储器（CAM）来提供映射功能。 重命名寄存器文件CAM还使用当前处理器状态信息来选择性地使标签比较器最小化访问寄存器的功率。 当标签比较器未使能时，它保持在低功率状态。 还描述了使用具有低功率特征的重命名寄存器文件的处理器。
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公开(公告)号：US20060190707A1
公开(公告)日：2006-08-24
申请号：US11061981
申请日：2005-02-18
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3861
摘要： When a branch misprediction in a pipelined processor is discovered, if the mispredicted branch instruction is not the last uncommitted instruction in the pipelines, older uncommitted instructions are checked for dependency on a long latency operation. If one is discovered, all uncommitted instructions are flushed from the pipelines without waiting for the dependency to be resolved. The branch prediction is corrected, and the branch instruction and all flushed instructions older than the branch instruction are re- fetched and executed.
摘要翻译： 当发现流水线处理器中的分支错误预测时，如果错误的分支指令不是管道中的最后一条未提交的指令，则会检查较长的未提交的指令对长时间延迟操作的依赖性。 如果被发现，所有未提交的指令都将从管道中刷新，而不必等待解决依赖关系。 校正分支预测，并重新执行分支指令和比分支指令更早的所有刷新指令。
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8.发明申请Conditional instruction execution via emissary instruction for condition evaluation 有权有条件的指令通过使用指令执行条件评估公开(公告)号：US20060179288A1
公开(公告)日：2006-08-10
申请号：US11055919
申请日：2005-02-10
IPC分类号： G06F9/44
CPC分类号： G06F9/3867 , G06F9/30072 , G06F9/3017 , G06F9/30181 , G06F9/3824 , G06F9/3826
摘要： Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the condition and an unconditional base instruction operative to perform the operation. The emissary instruction is executed, while the base instruction is halted. The emissary instruction evaluates the condition and reports the condition evaluation back to the base instruction. Based on the condition evaluation, the base instruction is either launched into the pipeline for execution, or it is discarded (or a NOP, or null instruction, substituted for it). In either case, the dependencies of following instructions may be resolved.
摘要翻译： 通过转换条件指令来简化危险检测，条件指令可操作以在满足条件的情况下执行操作到可操作以评估条件的执行指令和用于执行操作的无条件基准指令。 在基本指令停止的情况下执行执行指令。 使者指令评估条件并将条件评估报告回基本指令。 基于条件评估，基本指令要么被启动到管道中才能执行，要么被丢弃（或者一个NOP或者空的指令代替它）。 在任一情况下，可以解决以下指令的依赖性。
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9.发明申请Translation look aside buffer (TLB) with increased translational capacity for multi-threaded computer processes 失效翻译看起来缓冲区（TLB）具有增加的多线程计算机进程的平移能力公开(公告)号：US20050108497A1
公开(公告)日：2005-05-19
申请号：US10714282
申请日：2003-11-14
申请人： Jeffrey Bridges , Les DeBruyne , Robert Goldiez , Michael McIlvaine , Thomas Sartorius , Rodney Smith
发明人： Jeffrey Bridges , Les DeBruyne , Robert Goldiez , Michael McIlvaine , Thomas Sartorius , Rodney Smith
CPC分类号： G06F12/1036 , G06F9/342 , G06F9/3851
摘要： Method and apparatus for increasing the number of real memory addresses accessible through a translational look-aside buffer (TLB) by a multi thread CPU. The buffer entries include a virtual address, a real address and a special mode bit indicating whether the address represents one of a plurality of threads being processed by the CPU. If the special mode bit is set, the real address associated with the virtual address higher order bits are concatenated with the thread identification number being processed to obtain a real address. Buffer entries containing no special mode bit, or special mode bit set to 0, are processed by using the full length of the real address associated with the virtual address stored in the look-aside buffer (TLB).
摘要翻译： 用于通过多线程CPU通过翻译后备缓冲器（TLB）来访问的实际存储器地址的数量的方法和装置。 缓冲器条目包括虚地址，实地址和特殊模式位，指示地址是否表示CPU正在处理的多个线程中的一个。 如果设置了特殊模式位，则与虚拟地址较高位相关联的实际地址与被处理的线程标识号连接以获得实际地址。 通过使用与存储在后备缓冲区（TLB）中的虚拟地址相关联的实际地址的全长处理不包含特殊模式位或特殊模式位设置为0的缓冲区条目。
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10.发明申请公开(公告)号：US20050060518A1
公开(公告)日：2005-03-17
申请号：US10664384
申请日：2003-09-17
CPC分类号： G06F9/3836 , G06F9/3826 , G06F9/3851
摘要： A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.
摘要翻译： 一种用于优化微处理器中能够同时处理多个指令线程的吞吐量的方法。 在输入缓冲器和微处理器的流水线之间提供指令发生逻辑。 指令问题逻辑根据当指令到达需要的流水线中的阶段时，基于所需操作数将可用的概率来推测来自给定线程的指令。 如果当前流水线条件表明指令需要在共享资源中停止以等待操作数的重要概率，则指令的发出被阻止。 一旦指令停顿的概率低于某个阈值，则根据当前流水线条件，允许发出指令。
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