公开(公告)号：US5794070A

公开(公告)日：1998-08-11

申请号：US730777

申请日：1996-10-16

申请人： Jeffrey L. Rabe ,  Dave Smyth ,  David D. Lent ,  Sathyamurthi Sadhasivan ,  Dahmane Dahmani ,  Stephen T. Rowland ,  James S. Coke ,  Mitchell W. Dale

发明人： Jeffrey L. Rabe ,  Dave Smyth ,  David D. Lent ,  Sathyamurthi Sadhasivan ,  Dahmane Dahmani ,  Stephen T. Rowland ,  James S. Coke ,  Mitchell W. Dale

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： A computer system comprises a direct memory access (DMA) transfer unit and a plurality of DMA devices coupled by an external bus. The DMA transfer unit effectuates DMA transfers for the plurality of DMA devices. The DMA transfer unit contains a DMA controller, a bus arbiter, and a bus controller. The DMA controller and the bus controller generate a two-clock cycle DMA transfer. To effectuate a two-clock cycle DMA transfer, a requesting DMA device sets-up a DMA transfer with the DMA controller such that a DACK# signal is asserted during a first clock period. During a second clock period, the DMA controller sets-up the memory address. During a third clock period, the bus controller transitions a command signal on the external bus. Upon assertion of the command signal, valid data is asserted on the external bus. For demand and block mode operations, additional DMA transfers are executed in a two-clock cycle DMA transfer. The DMA controller and the bus controller also generate a three-clock cycle DMA transfer.

摘要翻译： 计算机系统包括直接存储器访问（DMA）传送单元和通过外部总线耦合的多个DMA设备。 DMA传送单元为多个DMA设备实现DMA传输。 DMA传输单元包含DMA控制器，总线仲裁器和总线控制器。 DMA控制器和总线控制器产生一个两个时钟周期的DMA传输。 为了实现双时钟周期DMA传输，请求的DMA设备与DMA控制器建立DMA传输，使得在第一时钟周期期间断言DACK＃信号。 在第二个时钟周期内，DMA控制器设置存储器地址。 在第三个时钟周期内，总线控制器转换外部总线上的命令信号。 在断言命令信号时，有效数据在外部总线上被断言。 对于需求和块模式操作，在两个时钟周期的DMA传输中执行额外的DMA传输。 DMA控制器和总线控制器也产生三个时钟周期的DMA传输。