摘要:
A display device includes a display module, an outer housing, a glass cover and a strength-enhanced member. The display module is installed within the outer housing, and the outer housing has a support portion. The glass cover is attached to the support portion. The strength-enhanced member is located within the outer housing, and the strength-enhanced member is disposed closer to a corresponding corner of the outer housing than a corresponding corner of the glass cover is.
摘要:
This invention describes a programmable, digital implementation to shift an arbitrary frequency, or various frequencies in various communication systems of the original signal in the frequency domain. The correspondent phase accumulation to perform the desired frequency shift per sampling instant is perfectly tracked by counting up or down a simple integer. Several arbitrary frequency shifters with different mathematical models are provided. The correspondent implementations with Look-Up-Tables (LUT) are derived for high-speed implementations without further calculations of the values of the sine and cosine functions every sampling instant. Furthermore, a simple shift-and-add phase rotation is described to replace the four required real multiplications. If the original complex signal contains only one-bit each from real part and imaginary part, a surprisingly simple implementation is derived and disclosed for the overall arbitrary frequency shift operation. Further simplifications are also disclosed to make this invention feasible for high sampling frequencies and small frequency drifts.
摘要:
The present invention discloses apparatus and method for fast and robust automatic gain control (AGC). By using the power statistics and/or the amplitude statistics of multiple pairs of signed ADC outputs, the additional gain control can be determined and included in a statistics-aided AGC to successfully complete the AGC function for a received signal having a dynamic range up to 100 dB within a few micro-seconds.
摘要:
The present invention relates to an adaptive, cost-performance efficient, power-saving apparatus for wireless communication systems, such as but not limited to Bluetooth (BT) receivers, and in particular to a packet-based receiver's decoding algorithm which can detect the presence or absence of the adjacent channel interference (ACI) before the scheduled starting time for receiving a Bluetooth packet, and accordingly set the receiver configurations including the filter's pass-band bandwidth (BW), filter's order, the sampling rate, the number of analog-to-digital-converter (ADC) output bits, and the automatic-gain-control (AGC) algorithm unit to determine the low noise amplifier (LNA) and variable gain amplifier (VGA) settings.
摘要:
An acquisition scheme for receiving a Bluetooth basic data rate (BDR) or enhanced data rate (EDR) packet. A simplified acquisition apparatus for a Bluetooth receiver having a phase differentiator, a plurality of basic building blocks, a plurality of 1-bit switch, and a correlation computation equation. It features a simplified acquisition circuit implementation with a 1-bit correlator hardware shared by access code and EDR synchronization sequence correlation computations. A 4 MHz sampling rate is used for correlation computation. A SINC interpolator is then used to get an 8 or 16 MHz timing resolution for data bit decoding. Based on the measurement results, this simple acquisition scheme can support successful decoding of a received Bluetooth packet with a maximum timing offset of +/−40 ppm and a maximum frequency offset of +/−60 ppm without loss of receiver sensitivity.
摘要:
The present invention discloses a generating method for short training field in IEEE 802.11n communication systems, mainly comprising the steps of: storing only a first set of time-domain HT-STF sequences in the memory; and deriving a second set of the time-domain HT-STF sequences from the first set of the time-domain HT-STF sequences. The first set of time-domain HT-STF sequences is the time-domain HT-STF sequences either for lower 20 MHz of 40 MHz BW or upper 20 MHz of 40 MHz BW. According to the invention, it is shown that only one set of time-domain HT-STF sequence needs to be stored in the memory. The other three sets of time-domain HT-STF sequence can be generated easily from simple calculation. Therefore, the saving in buffer size to implement all four configurations is significant.