公开(公告)号：US07586802B2

公开(公告)日：2009-09-08

申请号：US12027333

申请日：2008-02-07

申请人： Jer-Hau Hsu ,  Fu-Nian Liang ,  Yufe-Feng Lin

发明人： Jer-Hau Hsu ,  Fu-Nian Liang ,  Yufe-Feng Lin

IPC分类号： G11C7/00

CPC分类号： G11C7/12

摘要： A memory is provided. The memory includes a memory cell, a clamp transistor, an inverter, a bit line, a pre-charge path and a detector and controller circuit. The memory is coupled to the clamp transistor. The clamp transistor has a first end, a second end and a control end. The inverter has an input end electrically connected to the second end of the clamp transistor and an output end electrically connected to the control end of the clamp transistor. The bit line is electrically connected to the second end of the clamp transistor and the input end of the inverter and has a bit-line voltage thereon. The pre-charge path is electrically connected to the first end of the clamp transistor through a node having a sensing voltage thereon. The detector and controller circuit is electrically connected to the first end of the clamp transistor and the pre-charge path for detecting the sensing voltage in order to open the pre-charge path to raise the bit-line voltage when the sensing voltage is at a low level and close the pre-charge path when the sensing voltage is at a high level.

摘要翻译： 提供记忆。 存储器包括存储单元，钳位晶体管，反相器，位线，预充电路径以及检测器和控制器电路。 存储器耦合到钳位晶体管。 钳位晶体管具有第一端，第二端和控制端。 逆变器具有电连接到钳位晶体管的第二端的输入端和电连接到钳位晶体管的控制端的输出端。 位线电连接到钳位晶体管的第二端和反相器的输入端，并在其上具有位线电压。 预充电路径通过其上具有感测电压的节点电连接到钳位晶体管的第一端。 检测器和控制器电路电连接到钳位晶体管的第一端和用于检测感测电压的预充电路径，以便当感测电压为一个时，打开预充电路径以升高位线电压 低电平并且当感测电压处于高电平时闭合预充电路径。

公开(公告)号：US20090201747A1

公开(公告)日：2009-08-13

申请号：US12027333

申请日：2008-02-07

申请人： Jer-Hau Hsu ,  Fu-Nian Liang ,  Yufe-Feng Lin

发明人： Jer-Hau Hsu ,  Fu-Nian Liang ,  Yufe-Feng Lin

IPC分类号： G11C7/00

CPC分类号： G11C7/12

摘要： A memory is provided. The memory includes a memory cell, a clamp transistor, an inverter, a bit line, a pre-charge path and a detector and controller circuit. The memory is coupled to the clamp transistor. The clamp transistor has a first end, a second end and a control end. The inverter has an input end electrically connected to the second end of the clamp transistor and an output end electrically connected to the control end of the clamp transistor. The bit line is electrically connected to the second end of the clamp transistor and the input end of the inverter and has a bit-line voltage thereon. The pre-charge path is electrically connected to the first end of the clamp transistor through a node having a sensing voltage thereon. The detector and controller circuit is electrically connected to the first end of the clamp transistor and the pre-charge path for detecting the sensing voltage in order to open the pre-charge path to raise the bit-line voltage when the sensing voltage is at a low level and close the pre-charge path when the sensing voltage is at a high level.

摘要翻译： 提供记忆。 存储器包括存储单元，钳位晶体管，反相器，位线，预充电路径以及检测器和控制器电路。 存储器耦合到钳位晶体管。 钳位晶体管具有第一端，第二端和控制端。 逆变器具有电连接到钳位晶体管的第二端的输入端和电连接到钳位晶体管的控制端的输出端。 位线电连接到钳位晶体管的第二端和反相器的输入端，并在其上具有位线电压。 预充电路径通过其上具有感测电压的节点电连接到钳位晶体管的第一端。 检测器和控制器电路电连接到钳位晶体管的第一端和用于检测感测电压的预充电路径，以便当感测电压为一个时，打开预充电路径以升高位线电压 低电平并且当感测电压处于高电平时闭合预充电路径。

公开(公告)号：US08898439B2

公开(公告)日：2014-11-25

申请号：US12837823

申请日：2010-07-16

申请人： Kuen-Long Chang ,  Yufe-Feng Lin ,  Chun-Hsiung Hung

发明人： Kuen-Long Chang ,  Yufe-Feng Lin ,  Chun-Hsiung Hung

IPC分类号： G06F9/34 ,  G11C7/10 ,  G06F9/30 ,  G06F9/38

CPC分类号： G11C7/10 ,  G06F9/30149 ,  G06F9/342 ,  G06F9/3875

摘要： A serial flash memory and an address transmission method thereof. The serial flash memory selectively addresses a first memory space according to a first address length or addresses a second memory space according to a second address length longer than the first address length. If the first memory space is addressed according to the first address length, a first memory address is completely received within an address time duration so that data corresponding to the first memory address is initially outputted from a starting clock. In the address transmission method, if the second memory space is addressed according to the second address length, a portion of a second memory address is received within the address time duration. The other portion of the second memory address is received within a waiting time duration so that data corresponding to the second memory address is initially outputted from the starting clock.

摘要翻译： 串行闪存及其地址发送方法。 串行闪速存储器根据第一地址长度选择性地寻址第一存储器空间，或者根据长于第一地址长度的第二地址长度寻址第二存储器空间。 如果根据第一地址长度寻址第一存储器空间，则在地址持续时间内完全接收到第一存储器地址，从而从起始时钟开始输出与第一存储器地址对应的数据。 在地址发送方法中，如果根据第二地址长度寻址第二存储器空间，则在地址持续时间内接收第二存储器地址的一部分。 第二存储器地址的另一部分在等待时间段内被接收，使得对应于第二存储器地址的数据最初从起始时钟输出。

公开(公告)号：US20110016288A1

公开(公告)日：2011-01-20

申请号：US12837823

申请日：2010-07-16

申请人： Kuen-Long Chang ,  Yufe-Feng Lin ,  Chun-Hsiung Hung

发明人： Kuen-Long Chang ,  Yufe-Feng Lin ,  Chun-Hsiung Hung

IPC分类号： G06F12/06

CPC分类号： G11C7/10 ,  G06F9/30149 ,  G06F9/342 ,  G06F9/3875

摘要： A serial flash memory and an address transmission method thereof. The serial flash memory selectively addresses a first memory space according to a first address length or addresses a second memory space according to a second address length longer than the first address length. If the first memory space is addressed according to the first address length, a first memory address is completely received within an address time duration so that data corresponding to the first memory address is initially outputted from a starting clock. In the address transmission method, if the second memory space is addressed according to the second address length, a portion of a second memory address is received within the address time duration. The other portion of the second memory address is received within a waiting time duration so that data corresponding to the second memory address is initially outputted from the starting clock.

摘要翻译： 串行闪存及其地址发送方法。 串行闪速存储器根据第一地址长度选择性地寻址第一存储器空间，或者根据长于第一地址长度的第二地址长度寻址第二存储器空间。 如果根据第一地址长度寻址第一存储器空间，则在地址持续时间内完全接收到第一存储器地址，从而从起始时钟开始输出与第一存储器地址对应的数据。 在地址发送方法中，如果根据第二地址长度寻址第二存储器空间，则在地址持续时间内接收第二存储器地址的一部分。 第二存储器地址的另一部分在等待时间段内被接收，使得对应于第二存储器地址的数据最初从起始时钟输出。