SEMICONDUCTOR DEVICE WITH REDUCED STANDBY FAILURES
    1.
    发明申请
    SEMICONDUCTOR DEVICE WITH REDUCED STANDBY FAILURES 有权
    具有降低待机故障的半导体器件

    公开(公告)号:US20090154281A1

    公开(公告)日:2009-06-18

    申请号:US12235812

    申请日:2008-09-23

    CPC classification number: G11C5/14

    Abstract: A semiconductor memory device includes a cell core storing data, a plurality of peripheral circuit components, collectively driving data to/from the cell core and providing a default state at an output signal state during an initialization process upon power-up, and an initialization circuit detecting a standby mode of operation for the semiconductor memory device, and upon detecting the standby mode controlling operation of the plurality of peripheral circuit components to provide the default state as the signal state during standby mode.

    Abstract translation: 半导体存储器件包括:存储数据的单元核心,多个外围电路部件,共同地向单元核心驱动数据,并且在上电时的初始化处理期间以输出信号状态提供默认状态;以及初始化电路 检测半导体存储器件的待机操作模式,并且在检测到多个外围电路组件的待机模式控制操作时提供默认状态作为待机模式期间的信号状态。

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