Dual operating speed switchover arrangement for CPU
    2.
    发明授权
    Dual operating speed switchover arrangement for CPU 失效
    CPU的双工作速切换装置

    公开(公告)号:US4821229A

    公开(公告)日:1989-04-11

    申请号:US808394

    申请日:1985-12-12

    申请人: Luis H. Jauregui

    发明人: Luis H. Jauregui

    IPC分类号: G06F1/08 G06F1/00 G04G7/00

    CPC分类号: G06F1/08

    摘要: A user selectable switch arrangement in combination with logic circuitry allows the timing of a central processor unit (CPU) to be switched between two clock frequencies. Operation at a higher frequency permits the CPU to perform an increased number of tasks per unit time and thus increases data throughput, while a lower operating frequency provides enhanced CPU hardware and software interfacing compatibility.

    摘要翻译: 与逻辑电路组合的用户可选开关装置允许中央处理器单元(CPU)的定时在两个时钟频率之间切换。 更高频率的操作允许CPU每单位时间执行更多的任务,从而提高数据吞吐量,而较低的工作频率提供增强的CPU硬件和软件接口兼容性。