公开(公告)号：US08249616B2

公开(公告)日：2012-08-21

申请号：US11844006

申请日：2007-08-23

申请人： Joergen Boejer ,  Alain Vallauri ,  Ilyas Berk Guvelioglu

发明人： Joergen Boejer ,  Alain Vallauri ,  Ilyas Berk Guvelioglu

IPC分类号： H04Q7/20

CPC分类号： G01S19/12 ,  G01S19/09 ,  G01S19/235 ,  G01S2205/008 ,  H04B7/18532

摘要： A wireless circuit (1100, 1190) for tracking an incoming signal and for use in a network (2000) having handover from one part (Cell A) of the network to another part (Cell B). The wireless circuit includes a processor (CE 1100) responsive to the incoming signal, the processor (CE 1100) operable to generate pulse edges representing network-based receiver synchronization instances (RSIs), and a timekeeping circuitry (2420, 2430, 2450) including an oscillator circuitry (2162), the timekeeping circuitry (2420, 2430) operable to maintain a set of counter circuitries (2422-2428) including a counter circuitry (2422) operable to maintain at least one network time component based on the RSIs and another counter circuitry (2428) operable at least during handover and during loss of network coverage for maintaining at least one internal time component (NC) based on the oscillator circuitry (2162), the set of counter circuitries (2422-2428) operable to account for elapsing time substantially gaplessly and substantially without overlap between the time components during a composite of network coverage, loss of network coverage and handover, and the timekeeping circuitry further including a time generator (2450) for combining the time components from the set of counter circuitries (2422-2428) to generate an approximate absolute time (SGTB). Other electronic circuits, positioning systems, methods of operation, and processes of manufacture are also disclosed and claimed.

摘要翻译： 一种用于跟踪输入信号并用于具有从网络的一部分（小区A）到另一部分（小区B）的切换的网络（2000）中使用的无线电路（1100,1190）。 无线电路包括响应于输入信号的处理器（CE 1100），处理器（CE 1100）可操作以产生表示基于网络的接收机同步实例（RSI）的脉冲边缘，以及计时电路（2420,2430,2450），包括 振荡器电路（2162），所述计时电路（2420,2430）可操作以维持包括计数器电路（2422）的一组计数器电路（2422-2428），所述计数器电路可操作以基于所述RSI和另一个维护至少一个网络时间分量 计数器电路（2428）可操作至少在切换期间和在网络覆盖的丢失期间，用于基于振荡器电路（2162）维持至少一个内部时间分量（NC），该组计数器电路（2422-2428）可操作以解决 在网络覆盖的复合，网络覆盖和切换的丢失以及计时电路f之间的时间分量之间基本上无间隙地且基本上没有重叠的时间间隔 还包括用于组合来自所述一组计数器电路（2422-2428）的时间分量以产生近似绝对时间（SGTB）的时间发生器（2450）。 其他电子电路，定位系统，操作方法和制造方法也被公开并要求保护。

公开(公告)号：US20090054075A1

公开(公告)日：2009-02-26

申请号：US11844006

申请日：2007-08-23

申请人： Joergen Boejer ,  Alain Vallauri ,  Ilyas Berk Guvelioglu

发明人： Joergen Boejer ,  Alain Vallauri ,  Ilyas Berk Guvelioglu

IPC分类号： H04Q7/20

CPC分类号： G01S19/12 ,  G01S19/09 ,  G01S19/235 ,  G01S2205/008 ,  H04B7/18532

摘要： A wireless circuit (1100, 1190) for tracking an incoming signal and for use in a network (2000) having handover from one part (Cell A) of the network to another part (Cell B). The wireless circuit includes a processor (CE 1100) responsive to the incoming signal, the processor (CE 1100) operable to generate pulse edges representing network-based receiver synchronization instances (RSIs), and a timekeeping circuitry (2420, 2430, 2450) including an oscillator circuitry (2162), the timekeeping circuitry (2420, 2430) operable to maintain a set of counter circuitries (2422-2428) including a counter circuitry (2422) operable to maintain at least one network time component based on the RSIs and another counter circuitry (2428) operable at least during handover and during loss of network coverage for maintaining at least one internal time component (NC) based on the oscillator circuitry (2162), the set of counter circuitries (2422-2428) operable to account for elapsing time substantially gaplessly and substantially without overlap between the time components during a composite of network coverage, loss of network coverage and handover, and the timekeeping circuitry further including a time generator (2450) for combining the time components from the set of counter circuitries (2422-2428) to generate an approximate absolute time (SGTB). Other electronic circuits, positioning systems, methods of operation, and processes of manufacture are also disclosed and claimed.

摘要翻译： 一种用于跟踪输入信号并用于具有从网络的一部分（小区A）到另一部分（小区B）的切换的网络（2000）中使用的无线电路（1100,1190）。 无线电路包括响应于输入信号的处理器（CE 1100），处理器（CE 1100）可操作以产生表示基于网络的接收机同步实例（RSI）的脉冲边缘，以及计时电路（2420,2430,2450），包括 振荡器电路（2162），所述计时电路（2420,2430）可操作以维持包括计数器电路（2422）的一组计数器电路（2422-2428），所述计数器电路可操作以基于所述RSI和另一个维护至少一个网络时间分量 计数器电路（2428）可操作至少在切换期间和在网络覆盖的丢失期间，用于基于振荡器电路（2162）维持至少一个内部时间分量（NC），该组计数器电路（2422-2428）可操作以解决 在网络覆盖的复合，网络覆盖和切换的丢失以及计时电路f之间的时间分量之间基本上无间隙地且基本上没有重叠的时间间隔 还包括用于组合来自所述一组计数器电路（2422-2428）的时间分量以产生近似绝对时间（SGTB）的时间发生器（2450）。 其他电子电路，定位系统，操作方法和制造方法也被公开并要求保护。

公开(公告)号：US08805376B2

公开(公告)日：2014-08-12

申请号：US13569335

申请日：2012-08-08

申请人： Joergen Boejer ,  Alain Vallauri ,  Ilyas Berk Guvelioglu

发明人： Joergen Boejer ,  Alain Vallauri ,  Ilyas Berk Guvelioglu

IPC分类号： H04W24/00

CPC分类号： G01S19/12 ,  G01S19/09 ,  G01S19/235 ,  G01S2205/008 ,  H04B7/18532

摘要： An electronic circuit for use with time of arrival signals from a network, including a position determination unit, a first clock, a second clock, and processing circuitry coupled to said first clock, said second clock, and said position determination unit. The processing circuitry is operable to project a relatively-accurate subsequent global time based on said first and second clocks and to then return said relatively-accurate subsequent global time to said position determination unit to facilitate a subsequent position determination by said position determination unit.

摘要翻译： 一种用于来自网络的到达时间信号的电子电路，包括位置确定单元，第一时钟，第二时钟以及耦合到所述第一时钟，所述第二时钟和所述位置确定单元的处理电路。 处理电路可操作以基于所述第一和第二时钟投射相对精确的后续全局时间，然后将所述相对准确的后续全局时间返回到所述位置确定单元，以便于由所述位置确定单元进行随后的位置确定。

公开(公告)号：US20130035099A1

公开(公告)日：2013-02-07

申请号：US13569335

申请日：2012-08-08

申请人： Joergen Boejer ,  Alain Vallauri ,  Ilyas Berk Guvelioglu

发明人： Joergen Boejer ,  Alain Vallauri ,  Ilyas Berk Guvelioglu

IPC分类号： H04W24/00 ,  H04W36/00

CPC分类号： G01S19/12 ,  G01S19/09 ,  G01S19/235 ,  G01S2205/008 ,  H04B7/18532

摘要： An electronic circuit for use with time of arrival signals from a network, including a position determination unit, a first clock, a second clock, and processing circuitry coupled to said first clock, said second clock, and said position determination unit. The processing circuitry is operable to project a relatively-accurate subsequent global time based on said first and second clocks and to then return said relatively-accurate subsequent global time to said position determination unit to facilitate a subsequent position determination by said position determination unit.

摘要翻译： 一种用于来自网络的到达时间信号的电子电路，包括位置确定单元，第一时钟，第二时钟以及耦合到所述第一时钟，所述第二时钟和所述位置确定单元的处理电路。 处理电路可操作以基于所述第一和第二时钟投射相对精确的后续全局时间，然后将所述相对准确的后续全局时间返回到所述位置确定单元，以便于由所述位置确定单元进行随后的位置确定。

公开(公告)号：US06049574A

公开(公告)日：2000-04-11

申请号：US61880

申请日：1998-04-17

申请人： Joseph Patrick Noonan ,  Ilyas Berk Guvelioglu ,  Premkumar Natarajan

发明人： Joseph Patrick Noonan ,  Ilyas Berk Guvelioglu ,  Premkumar Natarajan

IPC分类号： G06K9/62 ,  H04L25/03 ,  H03K5/01 ,  H04B1/06

CPC分类号： H04L25/0305 ,  H04L2025/03477 ,  H04L2025/0363

摘要： A technique for the blind equalization of digital communications channels relies on the iterative minimization of a cost function known as the J-divergence between a known or assumed probability density function (PDF) of the source data signal and an estimated PDF of a receiver decision output signal derived from the equalizer output signal by minimum-distance mapping. The J-divergence function is defined in terms of the Kullback-Leibler distance between the two PDFs. Minimization is achieved by continually updating both an equalizer tap coefficient vector and the estimated PDF of the decision output signal using a stochastic gradient algorithm applied to the J-divergence cost function.

摘要翻译： 用于数字通信信道的盲均衡的技术依赖于成本函数的迭代最小化，称为源数据信号的已知或假定的概率密度函数（PDF）与接收机决策输出的估计PDF之间的J分散 通过最小距离映射从均衡器输出信号中得到的信号。 J分散函数根据两个PDF之间的Kullback-Leibler距离来定义。 通过使用应用于J发散成本函数的随机梯度算法不断更新均衡器抽头系数向量和判定输出信号的估计PDF来实现最小化。