公开(公告)号：US08037437B2

公开(公告)日：2011-10-11

申请号：US12353168

申请日：2009-01-13

申请人： John D. Davis ,  Mihai Budiu ,  Hari Kannan

发明人： John D. Davis ,  Mihai Budiu ,  Hari Kannan

IPC分类号： G06F9/455

CPC分类号： G06F17/5031 ,  G06F17/5059 ,  G06F2217/84

摘要： The Global Dynamic Critical Path is used to optimize the design of a system-on-a-chip (SoC), where hardware modules are in different clock domains. Control signal transitions of the hardware modules are analyzed to identify the Global Dynamic Critical Path. Rules are provided for handling specific situations such as when concurrent input control signals are received by a hardware module. A configuration of the hardware modules is modified in successive iterations to converge at an optimum design, based on a cost function. The cost function can account for processing time as well as other metrics, such as power consumed. For example, during the iterations, hardware modules which are in the Global Dynamic Critical Path can have their clock speed increased and/or additional resources can be added, while hardware modules which are not in the Global Dynamic Critical Path can have their clock speed decreased and/or unnecessary resources can be removed.

摘要翻译： 全局动态关键路径用于优化片上系统（SoC）的设计，其中硬件模块位于不同的时钟域。 分析硬件模块的控制信号转换，以识别全局动态关键路径。 提供了处理特定情况的规则，例如当并发输入控制信号被硬件模块接收时。 基于成本函数，硬件模块的配置在连续迭代中被修改以在最佳设计下收敛。 成本函数可以解决处理时间以及其他指标，如功耗。 例如，在迭代期间，处于全局动态关键路径中的硬件模块可以提高其时钟速度和/或添加其他资源，而不在全局动态关键路径中的硬件模块可以使其时钟速度降低 和/或不必要的资源可以被去除。

公开(公告)号：US20100180240A1

公开(公告)日：2010-07-15

申请号：US12353168

申请日：2009-01-13

申请人： John D. Davis ,  Mihai Budiu ,  Hari Kannan

发明人： John D. Davis ,  Mihai Budiu ,  Hari Kannan

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5059 ,  G06F2217/84

摘要： The Global Dynamic Critical Path is used to optimize the design of a system-on-a-chip (SoC), where hardware modules are in different clock domains. Control signal transitions of the hardware modules are analyzed to identify the Global Dynamic Critical Path. Rules are provided for handling specific situations such as when concurrent input control signals are received by a hardware module. A configuration of the hardware modules is modified in successive iterations to converge at an optimum design, based on a cost function. The cost function can account for processing time as well as other metrics, such as power consumed. For example, during the iterations, hardware modules which are in the Global Dynamic Critical Path can have their clock speed increased and/or additional resources can be added, while hardware modules which are not in the Global Dynamic Critical Path can have their clock speed decreased and/or unnecessary resources can be removed.

摘要翻译： 全局动态关键路径用于优化片上系统（SoC）的设计，其中硬件模块位于不同的时钟域。 分析硬件模块的控制信号转换以识别全局动态关键路径。 提供了处理特定情况的规则，例如当并发输入控制信号被硬件模块接收时。 基于成本函数，硬件模块的配置在连续迭代中被修改以在最佳设计下收敛。 成本函数可以解决处理时间以及其他指标，如功耗。 例如，在迭代期间，处于全局动态关键路径中的硬件模块可以提高其时钟速度和/或添加其他资源，而不在全局动态关键路径中的硬件模块可以使其时钟速度降低 和/或不必要的资源可以被去除。

公开(公告)号：US07921276B2

公开(公告)日：2011-04-05

申请号：US11726316

申请日：2007-03-21

申请人： Ramesh Illikkal ,  Hari Kannan ,  Ravishankar Iyer ,  Donald Newell ,  Jaideep Moses ,  Li Zhao

发明人： Ramesh Illikkal ,  Hari Kannan ,  Ravishankar Iyer ,  Donald Newell ,  Jaideep Moses ,  Li Zhao

IPC分类号： G06F12/10

CPC分类号： G06F12/126

摘要： In one embodiment, the present invention includes a translation lookaside buffer (TLB) having storage locations each including a priority indicator field to store a priority level associated with an agent that requested storage of the data in the TLB, and an identifier field to store an identifier of the agent, where the TLB is apportioned according to a plurality of priority levels. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有存储位置的翻译后备缓冲器（TLB），每个存储位置包括优先级指示符字段以存储与请求TLB中的数据存储的代理相关联的优先级，以及存储 代理商的标识符，其中TLB根据多个优先级分摊。 描述和要求保护其他实施例。

公开(公告)号：US20080235487A1

公开(公告)日：2008-09-25

申请号：US11726316

申请日：2007-03-21

申请人： Ramesh Illikkal ,  Hari Kannan ,  Ravishankar Iyer ,  Donald Newell ,  Jaideep Moses ,  Li Zhao

发明人： Ramesh Illikkal ,  Hari Kannan ,  Ravishankar Iyer ,  Donald Newell ,  Jaideep Moses ,  Li Zhao

IPC分类号： G06F9/34

CPC分类号： G06F12/126

摘要： In one embodiment, the present invention includes a translation lookaside buffer (TLB) having storage locations each including a priority indicator field to store a priority level associated with an agent that requested storage of the data in the TLB, and an identifier field to store an identifier of the agent, where the TLB is apportioned according to a plurality of priority levels. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有存储位置的翻译后备缓冲器（TLB），每个存储位置包括优先级指示符字段以存储与请求TLB中的数据存储的代理相关联的优先级，以及存储 代理商的标识符，其中TLB根据多个优先级分摊。 描述和要求保护其他实施例。

公开(公告)号：US20060013227A1

公开(公告)日：2006-01-19

申请号：US11140423

申请日：2005-05-27

申请人： Hari Kannan

发明人： Hari Kannan

IPC分类号： H04L12/28

CPC分类号： H04L67/1008 ,  H04L29/06 ,  H04L67/1002 ,  H04L67/1027 ,  H04L67/1034 ,  H04L69/16 ,  H04L69/164 ,  H04L2029/06054

摘要： A method and an apparatus for distributing a data packet sent by a computer via a connection line to a cluster system. The data packet comprises a UDP packet and an identification of the computer the data packet was sent from. After the data packet is received by an at least one second node the identification within said data packet is extracted. It will then be checked whether a data packet comprising the same identification has been previously received and forwarded to one of at least two first nodes. If that check is positive, the data packet is forwarded to one of those at least two first nodes. Otherwise, a new node is selected and the data packet is forwarded to that selected node for data processing. This allows high availability against failovers and also load balancing for UDP connections.

摘要翻译： 一种用于将由计算机经由连接线路发送的数据分组分发到集群系统的方法和装置。 数据分组包括UDP分组以及数据分组从其发送的计算机的标识。 在由至少一个第二节点接收到数据分组之后，提取所述数据分组内的标识。 然后将检查包括相同标识的数据分组是否已经被先前接收并转发到至少两个第一节点中的一个。 如果该检查是肯定的，则数据分组被转发到至少两个第一节点中的一个。 否则，选择一个新节点，并将数据包转发到该选定节点进行数据处理。 这样可以实现高可用性以及故障转移和UDP连接的负载平衡。