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1.发明授权Cab signal receiver demodulator employing redundant, diverse field programmable gate arrays 有权驾驶室信号接收机解调器采用冗余多样的现场可编程门阵列公开(公告)号：US07850127B2
公开(公告)日：2010-12-14
申请号：US12131381
申请日：2008-06-02
IPC分类号： G06F11/00
CPC分类号： G06F15/17
摘要： A processor includes a first field programmable gate array (FPGA) having a first central processing unit (CPU) core programmed to perform a first function, and first programmable hardware logics (PHLs) programmed to perform a second function. A second FPGA includes a second CPU core programmed to perform a third function, and second PHLs programmed to perform a fourth function. A communication interface is between the first and second CPU cores. The first and second FPGAs are diverse. A portion of the first function communicates first information from the first CPU core to the second CPU core through the interface. A portion of the third function communicates second information from the second CPU core to the first CPU core through the interface, and, otherwise, the first function is substantially the same as the third function. The second function is substantially the same as the fourth function.
摘要翻译： 处理器包括具有被编程为执行第一功能的第一中央处理单元（CPU）核心的第一现场可编程门阵列（FPGA）和被编程为执行第二功能的第一可编程硬件逻辑（PHL）。 第二FPGA包括被编程为执行第三功能的第二CPU核心，以及被编程为执行第四功能的第二PHL。 通信接口位于第一和第二CPU内核之间。 第一个和第二个FPGA是多样的。 第一功能的一部分通过接口将第一信息从第一CPU内核传送到第二CPU内核。 第三功能的一部分通过接口将第二信息从第二CPU内核传送到第一CPU内核，否则第一功能与第三功能基本相同。 第二功能与第四功能基本相同。
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2.发明申请CAB SIGNAL RECEIVER DEMODULATOR EMPLOYING REDUNDANT, DIVERSE FIELD PROGRAMMABLE GATE ARRAYS 有权CAB信号接收器DEMODULATOR使用冗余，多个现场可编程门阵列公开(公告)号：US20090230255A1
公开(公告)日：2009-09-17
申请号：US12131381
申请日：2008-06-02
CPC分类号： G06F15/17
摘要： A processor includes a first field programmable gate array (FPGA) having a first central processing unit (CPU) core programmed to perform a first function, and first programmable hardware logics (PHLs) programmed to perform a second function. A second FPGA includes a second CPU core programmed to perform a third function, and second PHLs programmed to perform a fourth function. A communication interface is between the first and second CPU cores. The first and second FPGAs are diverse. A portion of the first function communicates first information from the first CPU core to the second CPU core through the interface. A portion of the third function communicates second information from the second CPU core to the first CPU core through the interface, and, otherwise, the first function is substantially the same as the third function. The second function is substantially the same as the fourth function.
摘要翻译： 处理器包括具有被编程为执行第一功能的第一中央处理单元（CPU）核心的第一现场可编程门阵列（FPGA）和被编程为执行第二功能的第一可编程硬件逻辑（PHL）。 第二FPGA包括被编程为执行第三功能的第二CPU核心，以及被编程为执行第四功能的第二PHL。 通信接口位于第一和第二CPU内核之间。 第一个和第二个FPGA是多样的。 第一功能的一部分通过接口将第一信息从第一CPU内核传送到第二CPU内核。 第三功能的一部分通过接口将第二信息从第二CPU内核传送到第一CPU内核，否则第一功能与第三功能基本相同。 第二功能与第四功能基本相同。
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3.发明授权公开(公告)号：US08458581B2
公开(公告)日：2013-06-04
申请号：US12579504
申请日：2009-10-15
IPC分类号： G06F11/00
CPC分类号： G06F11/167 , G06F11/1004 , G06F11/1625 , H04L1/0061
摘要： A system for serially transmitting vital data includes first and second processors to determine first and second data, a serial communication apparatus to input third data and output serial data based upon the third data, and a memory having first and second ports accessible by the first and second processors, a first memory writable by the first processor and readable by the second processor, and a second memory writable by the second processor and readable by the first processor. The first and second processors store the first and second data in the first and second memories, cooperatively agree that the first data corresponds to the second data, and responsively cause the apparatus to employ: one of the first and second data as the third data, or parts of the first and second data as the third data, and output the serial data based upon the third data.
摘要翻译： 用于串行传送重要数据的系统包括用于确定第一和第二数据的第一和第二处理器，基于第三数据输入第三数据并输出串行数据的串行通信装置，以及具有可由第一和第二数据访问的第一和第二端口的存储器， 第二处理器，由第一处理器可写并且可由第二处理器读取的第一存储器，以及由第二处理器写入并可由第一处理器读取的第二存储器。 第一和第二处理器将第一和第二数据存储在第一和第二存储器中，协同地认为第一数据对应于第二数据，并且响应地使得装置使用第一和第二数据之一作为第三数据， 或第一和第二数据的部分作为第三数据，并且基于第三数据输出串行数据。
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公开(公告)号：US20110090714A1
公开(公告)日：2011-04-21
申请号：US12579446
申请日：2009-10-15
申请人： JAMES P. BROWN , John E. Lemonovich , James C. Werner , William J. Moltz , Lawrence A. Weber , William A. Sharp
发明人： JAMES P. BROWN , John E. Lemonovich , James C. Werner , William J. Moltz , Lawrence A. Weber , William A. Sharp
IPC分类号： H02J1/00
CPC分类号： G06F11/0796 , G06F11/16
摘要： An output apparatus includes a first source of a first signal having a first state or a different second state; a second source of a second signal having a first state or a different second state; and a circuit structured to output a vital output including a first state when the first state of the first signal corresponds to the first state of the second signal and, otherwise, including a different second state. At least one of the first signal and the second signal is a static signal. The other one of the first signal having the first state and the second signal having the first state is a dynamic signal. When at least one of the first signal has the different second state of the first signal and the second signal has the different second state of the second signal, the vital output includes the different second state.
摘要翻译： 输出装置包括具有第一状态或不同第二状态的第一信号的第一源; 具有第一状态或不同第二状态的第二信号的第二源; 以及电路，其被构造为当所述第一信号的第一状态对应于所述第二信号的第一状态时输出包括第一状态的重要输出，否则包括不同的第二状态。 第一信号和第二信号中的至少一个是静态信号。 具有第一状态的第一信号和具有第一状态的第二信号中的另一个是动态信号。 当第一信号中的至少一个具有第一信号的不同的第二状态，而第二信号具有第二信号的不同的第二状态时，生命输出包括不同的第二状态。
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公开(公告)号：US08289734B2
公开(公告)日：2012-10-16
申请号：US12579446
申请日：2009-10-15
申请人： James P. Brown , John E. Lemonovich , James C. Werner , William J. Moltz , Lawrence A. Weber , William A. Sharp
发明人： James P. Brown , John E. Lemonovich , James C. Werner , William J. Moltz , Lawrence A. Weber , William A. Sharp
CPC分类号： G06F11/0796 , G06F11/16
摘要： An output apparatus includes a first source of a first signal having a first state or a different second state; a second source of a second signal having a first state or a different second state; and a circuit structured to output a vital output including a first state when the first state of the first signal corresponds to the first state of the second signal and, otherwise, including a different second state. At least one of the first signal and the second signal is a static signal. The other one of the first signal having the first state and the second signal having the first state is a dynamic signal. When at least one of the first signal has the different second state of the first signal and the second signal has the different second state of the second signal, the vital output includes the different second state.
摘要翻译： 输出装置包括具有第一状态或不同第二状态的第一信号的第一源; 具有第一状态或不同第二状态的第二信号的第二源; 以及电路，其被构造为当所述第一信号的第一状态对应于所述第二信号的第一状态时输出包括第一状态的重要输出，否则包括不同的第二状态。 第一信号和第二信号中的至少一个是静态信号。 具有第一状态的第一信号和具有第一状态的第二信号中的另一个是动态信号。 当第一信号中的至少一个具有第一信号的不同的第二状态，而第二信号具有第二信号的不同的第二状态时，生命输出包括不同的第二状态。
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6.发明授权Programmable logic apparatus employing shared memory, vital processor and non-vital communications processor, and system including the same 有权采用共享存储器，重要处理器和非重要通信处理器的可编程逻辑装置以及包含该处理器的系统公开(公告)号：US08543774B2
公开(公告)日：2013-09-24
申请号：US13079962
申请日：2011-04-05
IPC分类号： G06F12/00
CPC分类号： G06F15/17
摘要： A programmable logic apparatus includes a shared memory having a first port, a second port and a third port; a first vital processor interfaced to the first port of the shared memory; and a non-vital communications processor separated from the first vital processor in the programmable logic apparatus and interfaced to the second port of the shared memory. The third port of the shared memory is an external port structured to interface an external second vital processor.
摘要翻译： 一种可编程逻辑装置，包括具有第一端口，第二端口和第三端口的共享存储器; 连接到共享存储器的第一端口的第一重要处理器; 以及与可编程逻辑设备中的第一重要处理器分离并且与共享存储器的第二端口接口的非重要通信处理器。 共享内存的第三个端口是一个外部端口，用于连接外部第二重要处理器。
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7.发明申请PROGRAMMABLE LOGIC APPARATUS EMPLOYING SHARED MEMORY, VITAL PROCESSOR AND NON-VITAL COMMUNICATIONS PROCESSOR, AND SYSTEM INCLUDING THE SAME 有权使用共享存储器的可编程逻辑设备，维护处理器和非通信通信处理器以及包括其的系统公开(公告)号：US20120260046A1
公开(公告)日：2012-10-11
申请号：US13079962
申请日：2011-04-05
IPC分类号： G06F12/00
CPC分类号： G06F15/17
摘要： A programmable logic apparatus includes a shared memory having a first port, a second port and a third port; a first vital processor interfaced to the first port of the shared memory; and a non-vital communications processor separated from the first vital processor in the programmable logic apparatus and interfaced to the second port of the shared memory. The third port of the shared memory is an external port structured to interface an external second vital processor.
摘要翻译： 一种可编程逻辑装置，包括具有第一端口，第二端口和第三端口的共享存储器; 连接到共享存储器的第一端口的第一重要处理器; 以及与可编程逻辑设备中的第一重要处理器分离并且与共享存储器的第二端口接口的非重要通信处理器。 共享内存的第三个端口是一个外部端口，用于连接外部第二重要处理器。
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8.发明授权
公开(公告)号：US6120453A
公开(公告)日：2000-09-19
申请号：US191433
申请日：1998-11-12
申请人： William A. Sharp
发明人： William A. Sharp
CPC分类号： A61B8/483 , A61B8/15 , A61B8/4245 , A61B8/4444 , A61B8/4477 , G01S15/8993 , Y10S128/916
摘要： Two or more ultrasound transducer probes applied to a body give information regarding the relative position of each by determining the time of transit of sound energy between each probe. Besides knowledge of the range from one probe to another, the orientation and bearing of one probe to the other is determined by calculating the relative direction by which sound energy arrives at a probe. By making the location of one of the probes be known through fixing it in space to a mechanical arm or similar mechanical device of knowable position, the absolute positions and orientations of both probes becomes known. Each of the two ultrasound probes may generate different views of the same structure. Such complimentary, and possibly simultaneous, views allow for greater precision and clearer three-dimensional images, as well as provide for more rapid accumulation of data. The primary application of this technology is to use an internal transesophageal and an external transabdominal probe to image the heart and nearby structures such as the aorta. However, this method could be applied to viewing any other area where ultrasound is able to be used to view that area from more than one location. One other example would be using one or more transabdominal probes as well as an intravaginal probe to create three-dimensional views of a fetus, the uterus and the ovaries.
摘要翻译： 应用于身体的两个或更多个超声换能器探针通过确定每个探针之间的声能的传递时间来给出关于每个的相对位置的信息。 除了从一个探针到另一个探针的范围的知识之外，通过计算声能到达探针的相对方向来确定一个探针到另一探针的方位和方位。 通过使其中一个探针的位置通过将其固定在空间中到具有可知位置的机械臂或类似的机械装置而已知，两个探针的绝对位置和取向已知。 两个超声探头中的每一个可以产生相同结构的不同视图。 这种互补和可能同时的视图允许更高的精度和更清晰的三维图像，并且提供更快速的数据累积。 该技术的主要应用是使用内部经食道和外部经腹探针对心脏和附近的结构（如主动脉）进行成像。 然而，该方法可以应用于观察任何其他区域，其中超声波能够用于从多于一个位置观看该区域。 另一个例子是使用一个或多个经腹探针以及阴道内探针来产生胎儿，子宫和卵巢的三维视图。
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