公开(公告)号：US20140065593A1

公开(公告)日：2014-03-06

申请号：US14015654

申请日：2013-08-30

申请人： John Gannon ,  Steven Platt

发明人： John Gannon ,  Steven Platt

IPC分类号： G09B3/06

CPC分类号： G09B3/06 ,  G09B7/06

摘要： The present invention relates to the field of automated evaluation, assessment and analysis. Disclosed is a method to create and store assignments, automatically analyze student accuracy and ability, and store analysis on individual students for an extended amount of time. This method can reduce the time and effort exerted by teachers in the creation and grading of assignments and more effectively analyzes student progress than any known software. An assessment software, “TEACH-TECH,” combined with a web-based database, “Cloud,” in the novel manner disclosed provides a means for substantially increasing the effectiveness of the educational system.

摘要翻译： 本发明涉及自动评估，评估和分析领域。 披露了一种创建和存储作业的方法，自动分析学生的准确性和能力，并在一段时间内对个别学生进行分析。 这种方法可以减少教师在创作和分配任务中所花费的时间和精力，并且比任何已知的软件更有效地分析学生进步。 评估软件“TEACH-TECH”结合网络数据库“Cloud”以公开的新颖方式提供了大幅提高教育系统有效性的手段。

公开(公告)号：US5426566A

公开(公告)日：1995-06-20

申请号：US826

申请日：1993-01-04

申请人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  Howard L. Kalter ,  Gordon A. Kelley, Jr. ,  Christopher P. Miller ,  Dale E. Pontius ,  Willem B. van der Hoeven ,  Steven Platt

发明人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  Howard L. Kalter ,  Gordon A. Kelley, Jr. ,  Christopher P. Miller ,  Dale E. Pontius ,  Willem B. van der Hoeven ,  Steven Platt

IPC分类号： H01L23/52 ,  H01L25/065 ,  H05K7/00

CPC分类号： H01L25/0657 ,  H01L25/0652 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/16195

摘要： Multichip integrated circuit packages and systems of multichip packages having reduced interconnecting lead lengths are disclosed. The multichip package includes a multiplicity of semiconductor chip layers laminated together in a unitized module. A first metallization pattern is connected to the integrated circuit chips on at least one side surface of the unitized module. In addition, at least one end surface of the module contains a second metallization pattern which is configured to facilitate connection of the package to an external signal source, such as another multichip package. The system includes at least two such packages which are electrically coupled via either metallization patterns provided on the end surface of the packagers. If required, a plurality of multichip packages can be directly coupled into the system in an analogous manner. Further specific details of the multichip package and the system of multichip packages are set forth herein.

摘要翻译： 公开了具有减小的互连引线长度的多芯片集成电路封装和多芯片封装的系统。 多芯片封装包括在单元化模块中层叠在一起的多个半导体芯片层。 第一金属化图案在集成模块的至少一个侧表面上连接到集成电路芯片。 此外，模块的至少一个端面包含第二金属化图案，其被配置为便于将封装件连接到诸如另一多芯片封装的外部信号源。 该系统包括至少两个这样的包装，其经由设置在包装机的端面上的金属化图案电耦合。 如果需要，可以以类似的方式将多个多芯片封装直接耦合到系统中。 本文阐述了多芯片封装和多芯片封装系统的进一步具体细节。