摘要:
In one embodiment, an Internet Protocol (IP) routing information base of a packet switching device is filtered to produce a significantly smaller subset of IP routes that are installed in one or more forwarding information bases for forwarding of IP packets. In one embodiment, these smaller forwarding information bases are located in memory local to a network processor to more quickly perform lookup operations thereon. In one embodiment, one or more of these forwarding information bases is used only for exact matching of addresses (not longest prefix matching). In one embodiment, the IP routes in these smaller forwarding information bases substantially correspond to packet switching devices in a network (e.g., core and edge routers), such as in contrast to including all the IP routes for devices external to the network.
摘要:
In one embodiment, an Internet Protocol (IP) routing information base of a packet switching device is filtered to produce a significantly smaller subset of IP routes that are installed in one or more forwarding information bases for forwarding of IP packets. In one embodiment, these smaller forwarding information bases are located in memory local to a network processor to more quickly perform lookup operations thereon. In one embodiment, one or more of these forwarding information bases is used only for exact matching of addresses (not longest prefix matching). In one embodiment, the IP routes in these smaller forwarding information bases substantially correspond to packet switching devices in a network (e.g., core and edge routers), such as in contrast to including all the IP routes for devices external to the network.
摘要:
A multilevel coupled policer is configured to police packets using at least two policing levels, including a first-level of class policers and a second-level aggregate policer. The multilevel coupled policer is configured to share bandwidth of the aggregate policer among packet traffic corresponding to the class policers based on the packet traffic. The multilevel coupled policer is configured to apply a particular class policer corresponding to a particular packet to identify a tentative policing action. The multilevel coupled policer is configured to apply the second-level aggregate policer to the particular packet based on the identified the tentative policing action and a result of a comparison operation of the number of tokens in one or more token buckets associated with the second-level aggregate policer and the length of the particular packet in order to determine a final policing action for marking and/or applying to the particular packet.
摘要:
A multilevel coupled policer is configured to police packets using at least two policing levels, including a first-level of class policers and a second-level aggregate policer. The multilevel coupled policer is configured to share bandwidth of the aggregate policer among packet traffic corresponding to the class policers based on the packet traffic. The multilevel coupled policer is configured to apply a particular class policer corresponding to a particular packet to identify a tentative policing action. The multilevel coupled policer is configured to apply the second-level aggregate policer to the particular packet based on the identified the tentative policing action and a result of a comparison operation of the number of tokens in one or more token buckets associated with the second-level aggregate policer and the length of the particular packet in order to determine a final policing action for marking and/or applying to the particular packet.
摘要:
A system and method for locally determining a fair allocated bandwidth for a network node configured to send and receive packets in an upstream direction and a downstream direction is disclosed. A local allocated bandwidth is allocated for locally generated network packets sent in the downstream direction. A minimum downstream available network bandwidth is determined from information received in the upstream direction. The local allocated bandwidth is adjusted based on the minimum downstream available network bandwidth and the local allocated bandwidth is used to govern whether a class of locally generated network packets are sent in the downstream direction.
摘要:
A system and method for locally determining a fair allocated bandwidth for a network node configured to send and receive packets in an upstream direction and a downstream direction is disclosed. A local allocated bandwidth is allocated for locally generated network packets sent in the downstream direction. A minimum downstream available network bandwidth is determined from information received in the upstream direction. The local allocated bandwidth is adjusted based on the minimum downstream available network bandwidth and the local allocated bandwidth is used to govern whether a class of locally generated network packets are sent in the downstream direction.
摘要:
A pluggable port adapter is used for connecting PCI devices to a host system through a PCI local bus while also adding functionality to the host system. The port adapter communicates with the host system through a port adapter/host interface that includes the PCI local bus and an auxiliary bus. The auxiliary bus is used for controlling the additional circuitry on the port adapter. A PROM on the adapter card is used for identifying the port adapter type, serial number and hardware revision. The auxiliary bus is used for conducting JTAG testing and is used by the host system to program logic devices on the port adapter. The logic devices can be reprogrammed in the field by the host system to repair bugs and to enhance performance and/or functionality. A power control circuit on the port adapter is controlled by the auxiliary bus for conducting hot swap operations.
摘要:
Methods and apparatus are disclosed for scheduling items (e.g., packets, processes, etc.) in a system, such as, but not limited to a computer or communications system (e.g., router, switch, etc.) In one implementation, multiple sets of items requiring processing to be performed are maintained. A current set of the multiple sets of items is identified. Each of the items in the current set is processed. In one implementation, this processing includes identifying a particular item in the current set, adding a quantum to a deficit of the particular item, processing an entity corresponding to the particular item, decreasing the deficit of the particular item by a value, determining if the deficit allows the particular item to be further processed, and moving the particular item from the current set to another of the multiple sets of items after said determining if deficit allows the particular item to be further processed.
摘要:
Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for scheduling items in a system, such as, but not limited to a computer or communications system. For example, in one implementation, each of the items in a set of items has an associated deficit and mini-deficit. A next particular item is selected from the set of items currently having enough deficit to process the particular item. One or more entities associated with the particular item is processed a commensurate amount corresponding to the mini-deficit associated with the particular item. This processing is repeatedly performed until there are no more entities associated with the particular item or until the deficit associated with the particular item does not allow any further processing at the current time.
摘要:
A pluggable port adapter is used for connecting PCI devices to a host system through a PCI local bus while also adding functionality to the host system. The port adapter communicates with the host system through a port adapter/host interface that includes the PCI local bus and an auxiliary bus. The auxiliary bus is used for controlling the additional circuitry on the port adapter. A PROM on the adapter card is used for identifying the port adapter type, serial number and hardware revision. The auxiliary bus is used for conducting JTAG testing and is used by the host system to program logic devices on the port adapter. The logic devices can be reprogrammed in the field by the host system to repair bugs and to enhance performance and/or functionality. A power control circuit on the port adapter is controlled by the auxiliary bus for conducting hot swap operations.