公开(公告)号：US07173851B1

公开(公告)日：2007-02-06

申请号：US11252461

申请日：2005-10-18

申请人： John M. Callahan ,  Hemanshu T. Vernenker ,  Michael D. Fliesler ,  Glen Arnold Rosendale ,  Harry Shengwen Luan ,  Zhongshang Liu

发明人： John M. Callahan ,  Hemanshu T. Vernenker ,  Michael D. Fliesler ,  Glen Arnold Rosendale ,  Harry Shengwen Luan ,  Zhongshang Liu

IPC分类号： G11C11/34

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said breakdown transistor. The gate of the write transistor is connected to a write wordline. Further, a first sense transistor has its gate connected to the sense node. A second sense transistor is connected in series to the first sense transistor and has its gate connected to a read wordline. The second sense transistor has its source connected to a column bitline.

摘要翻译： 形成在具有列位线和行字线的存储器阵列中有用的可编程存储器单元。 存储单元包括其栅极连接到程序字线的击穿晶体管和在感测节点处串联连接到所述击穿晶体管的写入晶体管。 写晶体管的栅极连接到写字线。 此外，第一感测晶体管的栅极连接到感测节点。 第二感测晶体管与第一感测晶体管串联连接，并且其栅极连接到读字线。 第二感测晶体管的源极连接到列位线。