公开(公告)号：US07646668B2

公开(公告)日：2010-01-12

申请号：US12058964

申请日：2008-03-31

申请人： John Udell ,  Richard Solomon ,  Eugene Saghi ,  Jeffrey K. Whitt

发明人： John Udell ,  Richard Solomon ,  Eugene Saghi ,  Jeffrey K. Whitt

IPC分类号： G11C8/00

CPC分类号： G06F5/06

摘要： Disclosed is a system that generates a write count value for indicating whether data can be read from a FIFO and a system that generates a read count value for indicating whether data can be written to a FIFO. Each of these systems operates in two separate clock domains. In the system that generates a write count value, write strobes are stored in parallel in a register in a first clock domain. The plurality of synchronizers trigger on a rising edge of the write strobe that is stored in the parallel register and generate an increment pulse in a second clock domain. An up/down counter reads the increment pulse in parallel and increments the up/down counter in parallel. A decrement signal from a read strobe decrements the up/down counter. The output of the counter is fed to a register that provides a write counter value to handshake logic that indicates whether data can be read from a FIFO without underflowing the FIFO.

摘要翻译： 公开了一种生成用于指示是否能够从FIFO读取数据的写入计数值的系统以及生成用于指示数据是否可以写入FIFO的读取计数值的系统。 这些系统中的每一个都在两个独立的时钟域中运行。 在产生写入计数值的系统中，写选通存储在第一时钟域中的寄存器中。 多个同步器在存储在并行寄存器中的写选通脉冲的上升沿触发，并在第二时钟域产生增量脉冲。 上/下计数器并行读取增量脉冲并并行增/减计数器。 来自读取选通的递减信号递减上/下计数器。 计数器的输出被馈送到寄存器，该寄存器为握手逻辑提供写计数值，该指令指示是否可以从FIFO读取数据，而不会使FIFO下溢。

公开(公告)号：US20090244993A1

公开(公告)日：2009-10-01

申请号：US12058964

申请日：2008-03-31

申请人： John Udell ,  Richard Solomon ,  Eugene Saghi ,  Jeffrey K. Whitt

发明人： John Udell ,  Richard Solomon ,  Eugene Saghi ,  Jeffrey K. Whitt

IPC分类号： G11C7/00

CPC分类号： G06F5/06

摘要： Disclosed is a system that generates a write count value for indicating whether data can be read from a FIFO and a system that generates a read count value for indicating whether data can be written to a FIFO. Each of these systems operates in two separate clock domains. In the system that generates a write count value, write strobes are stored in parallel in a register in a first clock domain. The plurality of synchronizers trigger on a rising edge of the write strobe that is stored in the parallel register and generate an increment pulse in a second clock domain. An up/down counter reads the increment pulse in parallel and increments the up/down counter in parallel. A decrement signal from a read strobe decrements the up/down counter. The output of the counter is fed to a register that provides a write counter value to handshake logic that indicates whether data can be read from a FIFO without underflowing the FIFO.

摘要翻译： 公开了一种生成用于指示是否能够从FIFO读取数据的写入计数值的系统以及生成用于指示数据是否可以写入FIFO的读取计数值的系统。 这些系统中的每一个都在两个独立的时钟域中运行。 在产生写入计数值的系统中，写选通存储在第一时钟域中的寄存器中。 多个同步器在存储在并行寄存器中的写选通脉冲的上升沿触发，并在第二时钟域产生增量脉冲。 上/下计数器并行读取增量脉冲并并行增/减计数器。 来自读取选通的递减信号递减上/下计数器。 计数器的输出被馈送到寄存器，该寄存器为握手逻辑提供写计数值，该指令指示是否可以从FIFO读取数据，而不会使FIFO下溢。

公开(公告)号：US07991927B2

公开(公告)日：2011-08-02

申请号：US12058984

申请日：2008-03-31

申请人： John Udell ,  Jeffrey K. Whitt

发明人： John Udell ,  Jeffrey K. Whitt

IPC分类号： G06F13/38

CPC分类号： G06F13/161

摘要： Disclosed is a store and forward device that reduces latency. The store and forward device allows front end devices having various transfer protocols to be connected in a single path through a RAM, while reducing latency. Front end devices that transfer data on a piecemeal basis are required to transfer all of the data to a RAM prior to downloading data to a back end. Front end devices that transfer data in a single download begin the transfer of data out of a RAM as soon as a threshold value is reached. Hence, the latency associated with downloading all of the data into a RAM 118 and then transferring all of the data out of the RAM is eliminated.

摘要翻译： 公开了一种减少延迟的存储和转发设备。 存储和转发设备允许具有各种传输协议的前端设备通过RAM连接在单个路径中，同时减少等待时间。 在将数据下载到后端之前，需要以零碎的方式传输数据的前端设备将所有数据传输到RAM。 一旦达到阈值，在单个下载中传输数据的前端设备开始将数据从RAM传送出去。 因此，消除了将所有数据下载到RAM 118中然后将所有数据从RAM中传出的相关延迟。

公开(公告)号：US20090248968A1

公开(公告)日：2009-10-01

申请号：US12058984

申请日：2008-03-31

申请人： John Udell ,  Jeffrey K. Whitt

发明人： John Udell ,  Jeffrey K. Whitt

IPC分类号： G06F12/00

CPC分类号： G06F13/161

摘要： Disclosed is a store and forward device that reduces latency. The store and forward device allows front end devices having various transfer protocols to be connected in a single path through a RAM, while reducing latency. Front end devices that transfer data on a piecemeal basis are required to transfer all of the data to a RAM prior to downloading data to a back end. Front end devices that transfer data in a single download begin the transfer of data out of a RAM as soon as a threshold value is reached. Hence, the latency associated with downloading all of the data into a RAM 118 and then transferring all of the data out of the RAM is eliminated.

摘要翻译： 公开了一种减少延迟的存储和转发设备。 存储和转发设备允许具有各种传输协议的前端设备通过RAM连接在单个路径中，同时减少等待时间。 在将数据下载到后端之前，需要以零碎的方式传输数据的前端设备将所有数据传输到RAM。 一旦达到阈值，在单个下载中传输数据的前端设备开始将数据从RAM传送出去。 因此，消除了将所有数据下载到RAM 118中然后将所有数据从RAM中传出的相关延迟。