摘要:
A method and apparatus for performing design verification is described. In one embodiment, a method for performing design verification includes specifying at least one object that represents at least one signal as a symbol in a design using a first command and instructing a symbolic simulator with the first command to treat the at least one object as a symbol.
摘要:
A method and apparatus for simulating a circuit is described. In one embodiment, the method comprises representing a plurality of identical components in a reduced form as a circuit having a single instance of the identical component with encoding for each input of the single instance to represent corresponding inputs to all of the plurality of identical components and decoding for each output port of the single instance to create output ports for the outputs associated with all of the plurality of identical components and symbolically simulating the reduced form of the circuit with simulation results being the same as results of symbolically simulating the plurality of identical components.
摘要:
A method and apparatus for simulating multiple stimuli using symbolic encoding. In one embodiment, the method comprises encoding a plurality of sets of stimulus to create a symbolic stimulus, symbolically simulating a device under test, including applying the symbolic stimulus to the device under test, and outputting a symbolic result from the device under test in response to the symbolic stimulus.