公开(公告)号：US20080133864A1

公开(公告)日：2008-06-05

申请号：US11566149

申请日：2006-12-01

申请人： Jonathan Randall Hinkle ,  Aaron Mitchell Richardson ,  Ganesh Balakrishnan

发明人： Jonathan Randall Hinkle ,  Aaron Mitchell Richardson ,  Ganesh Balakrishnan

IPC分类号： G06F12/06

CPC分类号： G06F12/0811 ,  G06F12/0804

摘要： An apparatus, system, and method are disclosed for caching fully buffered memory (FBM) data. A circuit card is connected to an FBM socket that is configured to receive a FBM. An interface module communicates with a memory controller and at least one FBM via the FBM socket through a plurality of electrical interfaces. A cache controller apportions memory space in the cache memory between each FBM of the at least one FBM according to an apportionment policy. A cache memory transparently stores data from the at least one FBM and the memory controller and transparently provides the data to the memory controller. The cache controller manages coherency between the at least one FBM and the cache memory.

摘要翻译： 公开了用于缓存全缓冲存储器（FBM）数据的装置，系统和方法。 电路卡连接到配置为接收FBM的FBM插座。 接口模块通过多个电接口经由FBM插座与存储器控制器和至少一个FBM通信。 缓存控制器根据分配策略来分配至少一个FBM的每个FBM之间的高速缓冲存储器中的存储器空间。 缓存存储器透明地存储来自至少一个FBM和存储器控制器的数据，并将数据透明地提供给存储器控制器。 高速缓存控制器管理至少一个FBM和高速缓冲存储器之间的一致性。