公开(公告)号：US06248654B1

公开(公告)日：2001-06-19

申请号：US09370880

申请日：1999-08-10

申请人： Joo-Young Lee ,  Yong Jik Park

发明人： Joo-Young Lee ,  Yong Jik Park

IPC分类号： H01L2144

CPC分类号： H01L21/76897

摘要： A method of forming a self-aligned contact in a semiconductor device comprising a semiconductor substrate and a gate line. The method comprises the steps of forming a conductive layer on an overall surface of the semiconductor substrate including the gate line, planarization-etching the conductive layer down to the gate line, and etching the conductive layer to form the contact, the etching performed at least until the contact is electrically separated from other portions of the conductive layer. The method may reduce or eliminate pad-to-gate electrode shorts by preventing exposure during etching of the gate electrode, reduce or eliminate pad-to-pad bridging by preventing generation of void regions, and reduce contact resistance by securing enough contact area between a pad and an active region in spite of misalignment of a photoresist pattern.

摘要翻译： 一种在包括半导体衬底和栅极线的半导体器件中形成自对准接触的方法。 该方法包括以下步骤：在包括栅极线的半导体衬底的整个表面上形成导电层，将导电层平坦化蚀刻到栅极线，并蚀刻导电层以形成接触，至少进行蚀刻 直到接触件与导电层的其它部分电分离。 该方法可以通过防止蚀刻栅电极期间的曝光来减少或消除焊盘对栅极电极的短路，通过防止产生空隙区域来减少或消除焊盘到焊盘桥接，并通过确保足够的接触面积来减小接触电阻 衬垫和有源区，尽管光致抗蚀剂图案未对准。