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1.发明授权Method and apparatus for transporting information to a graphic accelerator card 有权将信息传送到图形加速卡的方法和装置公开(公告)号：US06313845B1
公开(公告)日：2001-11-06
申请号：US09345678
申请日：1999-06-30
IPC分类号： G06F1300
CPC分类号： G06T17/00 , G06F9/3879 , G06T1/20
摘要： A graphics request stream is transferred from a host processor to a graphics card via a host bus so that the stream traverses the host bus no more than once. To that end, the graphics card has a graphics card memory, and the host processor has a host memory configured in a first memory configuration. The graphics card memory may be configured in the first memory configuration, and the graphics request stream is received directly in a message from the host processor (via the host bus). Upon receipt by the graphics card, the graphics request stream is written to the graphics card memory.
摘要翻译： 图形请求流通过主机总线从主机处理器传送到图形卡，使得数据流不超过一次地遍历主机总线。 为此，显卡具有图形卡存储器，并且主机处理器具有以第一存储器配置配置的主机存储器。 图形卡存储器可以被配置在第一存储器配置中，并且图形请求流被直接地从主处理器（经由主机总线）接收到消息中。 在由显卡接收时，图形请求流被写入图形卡存储器。
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公开(公告)号：US6046752A
公开(公告)日：2000-04-04
申请号：US246399
申请日：1999-02-09
CPC分类号： G06T1/20 , G06F15/7864
摘要： A graphics accelerator includes a plurality of digital signal processors that are arranged in a self-regulating, peer-to-peer configuration. Accordingly, the processors cooperate to process, on a cyclical basis, each of a successive series of graphics requests received over a request bus. To that end, each processor includes a request bus, an input in communication with the request bus, and an output coupled to a sequencer for ordering graphics requests processed by the digital signal processors.
摘要翻译： 一个图形加速器包括多个数字信号处理器，这些数字信号处理器被排列成一个自调节的点对点配置。 因此，处理器协作以循环的方式处理通过请求总线接收的连续的一系列图形请求中的每一个。 为此，每个处理器包括请求总线，与请求总线通信的输入，以及耦合到定序器的输出，用于排序由数字信号处理器处理的图形请求。
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