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公开(公告)号:US20060209613A1
公开(公告)日:2006-09-21
申请号:US11085693
申请日:2005-03-21
申请人: Brian Johnson , John Nerl , Ronald Bellomlo , Michael Day , Vicki Smith , Richard Schumacher , Rajakrishnan Radjassamy , June Goodwin
发明人: Brian Johnson , John Nerl , Ronald Bellomlo , Michael Day , Vicki Smith , Richard Schumacher , Rajakrishnan Radjassamy , June Goodwin
IPC分类号: G11C8/00
摘要: Embodiments of memory modules and corresponding methods are disclosed. One memory module embodiment includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second addressing register each having at least one of address and control input routing primarily provided in a first layer, the first addressing register coupled to the upper row of memory integrated circuits and the second addressing register coupled to the lower row of memory integrated circuits.
摘要翻译: 公开了存储器模块和相应方法的实施例。 一个存储器模块实施例包括印刷电路板,其包括上行存储器集成电路,下行存储器集成电路,以及第一寻址寄存器和第二寻址寄存器,第一寻址寄存器和第二寻址寄存器,每个至少具有 主要提供在第一层中的地址和控制输入路由之一,第一寻址寄存器耦合到上行存储器集成电路,第二寻址寄存器耦合到下行存储器集成电路。
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公开(公告)号:US20060245119A1
公开(公告)日:2006-11-02
申请号:US11108245
申请日:2005-04-18
申请人: June Goodwin , Michael Day , Brian Johnson , John Nerl , Richard Schumacher , Vicki Smith
发明人: June Goodwin , Michael Day , Brian Johnson , John Nerl , Richard Schumacher , Vicki Smith
IPC分类号: H02H7/00
CPC分类号: G11C5/14 , G11C5/04 , H05K1/0219 , H05K1/0231 , H05K1/0263 , H05K1/117 , H05K2201/09145
摘要: A memory module according to one implementation includes a support substrate, plural memory devices mounted on the support substrate, and pins having a predetermined arrangement on the support substrate, the pins comprising signal pins connected to the memory devices, power pins, and ground pins. In the predetermined arrangement of pins, each signal pin uses a ground pin as a reference, and each power pin is adjacent a ground pin for reduced impedance between the power pin and ground pin. In some implementations, some of the signal pins are associated with redundant pins.
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