公开(公告)号：US06530001B1

公开(公告)日：2003-03-04

申请号：US09419774

申请日：1999-10-18

申请人： Jung-Keun Lee

发明人： Jung-Keun Lee

IPC分类号： G06F1200

CPC分类号： G06F1/06

摘要： A computer system controlling a memory clock signal of a DIMM (dual in-line memory module) socket is described and which includes a processor controlling a 66 MHz or a 100 MHz system bus clock signal to be generated, a DIMM memory module supporting the 66 MHz or the 100 MH system bus clock signal, a clock generator generating the 66 MHz or the 100 MHz system bus clock signal by receiving control of the processor, a clock buffer, a first and a second system controllers. The clock generator and the clock buffer store setting data according to memory data of a memory module from a first system controller. The first and the second system controllers control a memory bus clock signal corresponding to an inserted single-sided type or double-sided type DIMM memory module to be outputted. As a result, a clock signal is cut off to an unused memory “model” module socket or an unused clock signal of a using memory module socket is cut off in response to “kind of an inserted” insertion of a memory module.

摘要翻译： 描述了控制DIMM（双列直插存储器模块）插座的存储器时钟信号的计算机系统，其包括控制要生成的66MHz或100MHz系统总线时钟信号的处理器，支持66 MHz或100 MH系统总线时钟信号，时钟发生器通过接收处理器的控制器，时钟缓冲器，第一和第二系统控制器来产生66MHz或100MHz系统总线时钟信号。 时钟发生器和时钟缓冲器根据来自第一系统控制器的存储器模块的存储器数据存储设置数据。 第一和第二系统控制器控制与插入的单面型或双面型DIMM存储器模块对应的存储器总线时钟信号，以输出。 结果，时钟信号被切断到未使用的存储器“模型”模块插座，或者响应于存储器模块的“插入”插入而切断使用存储器模块插座的未使用的时钟信号。