-
公开(公告)号：US20080177488A1
公开(公告)日：2008-07-24
申请号：US12058339
申请日：2008-03-28
CPC分类号： G01R21/133
摘要： Disclosed is a power consumption analysis method capable of reducing an analysis time of power consumption. The method is performed on a design circuit having a characteristic signal for specifying an operating mode of a circuit block and the method comprises the steps of: measuring an operating rate of the characteristic signal in each unit analysis interval for analyzing the power consumption; determining, based on measurement results of the operating rate of the characteristic signal, whether to measure the operating rate of the circuit block whose operating mode is specified by the characteristic signal; and measuring the operating rate of the circuit block only when determined to measure the operating rate of the circuit block.
摘要翻译： 公开了能够减少功耗的分析时间的功耗分析方法。 该方法在具有用于指定电路块的操作模式的特征信号的设计电路上执行，并且该方法包括以下步骤：测量每个单位分析间隔中的特征信号的工作速率，以分析功耗; 基于特征信号的运行速率的测量结果确定是否测量由特征信号指定操作模式的电路块的工作速率; 并且仅当确定测量电路块的工作速率时测量电路块的工作速率。
-
公开(公告)号：US08095354B2
公开(公告)日：2012-01-10
申请号：US11896943
申请日：2007-09-06
CPC分类号： G06F17/5022 , G06F17/5036
摘要： As a program tool of the embodiment estimating the peak of power consumption, primary processing is performed in which logic simulation is executed in a first time period to extract operation data of a gated clock for every predetermined section within the first time period, e.g. operation waveform data or data on the number of operations. Then, a narrowed section, which is composed of one or more sections and in which the switching activity per unit time is higher compared to other sections, is discovered, the switching activity being obtained from the operation data, and this narrowed section is taken as a second time period. Then, secondary processing is performed in which logic simulation is executed in the second time period to extract signal waveform data for every clock cycle and obtain power consumption data corresponding to the clock cycles from the extracted signal waveform data.
摘要翻译： 作为估计功耗峰值的实施例的程序工具，执行在第一时间段内执行逻辑模拟的第一处理，以在第一时间段内提取每个预定部分的门控时钟的操作数据，例如， 操作波形数据或操作次数的数据。 然后，发现由一个或多个部分组成并且其中每单位时间的切换活动与其他部分相比更高的变窄部分，从操作数据获得切换活动，并将该缩小部分视为 第二个时期。 然后，进行二次处理，其中在第二时间段中执行逻辑模拟以提取每个时钟周期的信号波形数据，并从所提取的信号波形数据中获得与时钟周期对应的功耗数据。
-
3.发明申请公开(公告)号：US20080127001A1
公开(公告)日：2008-05-29
申请号：US11907822
申请日：2007-10-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： A power consumption analyzing method, to be implemented by a computer, is for a circuit developing procedure that makes a logic design of the circuit in an RTL design stage and inserts a gated clock with respect to the circuit in a subsequent logic synthesis stage. The method comprises an extraction step, implemented by the computer, extracting a signal which is judged that it will be transformed into a gated clock in the logic synthesis stage, and storing the signal in a memory part, a measuring step, implemented by the computer, measuring an valid time of the signal stored in the memory part by a logic simulation, and storing the valid time in the memory part, and a post-simulation step, implemented by the computer, computing a power consumption analysis result of the circuit from the valid time stored in the memory part, a number of registers for each of modules that are function units forming the circuit, and a memory capacity coefficient indicating an extent to which a memory capacity within the circuit affects the power consumption of the circuit, and outputting the power consumption analysis result.
摘要翻译： 由计算机实现的功耗分析方法是用于在RTL设计阶段中进行电路的逻辑设计的电路开发过程，并且在随后的逻辑合成阶段中插入关于电路的门控时钟。 该方法包括由计算机实现的提取步骤，提取在逻辑合成级中判断为将其变换为门控时钟的信号，并将该信号存储在由计算机实现的存储器部分中的测量步骤 ，通过逻辑模拟测量存储在存储器部分中的信号的有效时间，并将有效时间存储在存储器部分中，以及由计算机实现的后仿真步骤，计算电路的功耗分析结果 存储在存储器部分中的有效时间，作为形成电路的功能单元的每个模块的寄存器数量以及指示电路内的存储器容量影响电路的功耗的程度的存储器容量系数，以及 输出功耗分析结果。
-
公开(公告)号：US07882458B2
公开(公告)日：2011-02-01
申请号：US11907822
申请日：2007-10-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： A power consumption analyzing method, to be implemented by a computer, is for a circuit developing procedure that makes a logic design of the circuit in an RTL design stage and inserts a gated clock with respect to the circuit in a subsequent logic synthesis stage. The method comprises an extraction step, implemented by the computer, extracting a signal which is judged that it will be transformed into a gated clock in the logic synthesis stage, and storing the signal in a memory part, a measuring step, implemented by the computer, measuring an valid time of the signal stored in the memory part by a logic simulation, and storing the valid time in the memory part, and a post-simulation step, implemented by the computer, computing a power consumption analysis result of the circuit from the valid time stored in the memory part, a number of registers for each of modules that are function units forming the circuit, and a memory capacity coefficient indicating an extent to which a memory capacity within the circuit affects the power consumption of the circuit, and outputting the power consumption analysis result.
摘要翻译： 由计算机实现的功耗分析方法是用于在RTL设计阶段中进行电路的逻辑设计的电路开发过程，并且在随后的逻辑合成阶段中插入关于电路的门控时钟。 该方法包括由计算机实现的提取步骤，提取在逻辑合成级中判断为将其变换为门控时钟的信号，并将该信号存储在由计算机实现的存储器部分中的测量步骤 ，通过逻辑模拟测量存储在存储器部分中的信号的有效时间，并将有效时间存储在存储器部分中，以及由计算机实现的后仿真步骤，计算电路的功耗分析结果 存储在存储器部分中的有效时间，作为形成电路的功能单元的每个模块的寄存器数量以及指示电路内的存储器容量影响电路的功耗的程度的存储器容量系数，以及 输出功耗分析结果。
-
公开(公告)号：US20080059923A1
公开(公告)日：2008-03-06
申请号：US11849999
申请日：2007-09-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A logic simulation is executed for a first netlist, activity rate data is determined for the gated clock buffer, the power consumption is calculated from the activity rate data. Thereafter, given a modified second netlist having at least a portion of the cells of the first netlist, activity rate data for the second netlist is determined from activity rate data for the first netlist, based on the correspondence relation between the gated clock buffers for the first and second netlists. The power consumption is calculated from the activity rate data thus determined. By this means, the power consumption can be estimated for the second netlist without again performing a logic simulation.
摘要翻译： 对第一网表执行逻辑模拟，为门控时钟缓冲器确定活动速率数据，根据活动率数据计算功耗。 此后，给定具有第一网表的小区的至少一部分的修改后的第二网表，基于第一网表的选通时钟缓冲器之间的对应关系，确定第二网表的活动率数据， 第一和第二个网页表。 从这样确定的活动率数据计算功耗。 通过这种方式，可以对第二网表估计功耗，而不再进行逻辑仿真。
-
公开(公告)号：US07900172B2
公开(公告)日：2011-03-01
申请号：US12058339
申请日：2008-03-28
IPC分类号： G06F17/50
CPC分类号： G01R21/133
摘要： Disclosed is a power consumption analysis method capable of reducing an analysis time of power consumption. The method is performed on a design circuit having a characteristic signal for specifying an operating mode of a circuit block and the method comprises the steps of: measuring an operating rate of the characteristic signal in each unit analysis interval for analyzing the power consumption; determining, based on measurement results of the operating rate of the characteristic signal, whether to measure the operating rate of the circuit block whose operating mode is specified by the characteristic signal; and measuring the operating rate of the circuit block only when determined to measure the operating rate of the circuit block.
摘要翻译： 公开了能够减少功耗的分析时间的功耗分析方法。 该方法在具有用于指定电路块的操作模式的特征信号的设计电路上执行，并且该方法包括以下步骤：测量每个单位分析间隔中的特征信号的工作速率，以分析功耗; 基于特征信号的运行速率的测量结果确定是否测量由特征信号指定操作模式的电路块的工作速率; 并且仅当确定测量电路块的工作速率时测量电路块的工作速率。
-
7.发明授权公开(公告)号：US09021289B2
公开(公告)日：2015-04-28
申请号：US13273837
申请日：2011-10-14
申请人： Takayuki Sasaki , Hirohisa Kotegawa , Takashi Tokue , Shigeru Satoh , Tatsuro Miyakawa , Ryuji Fujita , Junichi Niitsuma
发明人： Takayuki Sasaki , Hirohisa Kotegawa , Takashi Tokue , Shigeru Satoh , Tatsuro Miyakawa , Ryuji Fujita , Junichi Niitsuma
CPC分类号： G06F17/504 , G06F2217/78
摘要： In a power estimator, a power coefficient-calculating section acquires an average value of the number of signal changes per unit time in each circuit range to thereby calculate a power coefficient for each circuit range or calculate a power coefficient for each circuit range when the average value of the number of signal changes per unit time is equal to 1, a correction coefficient-calculating section calculates a ratio of an average value of the number of signal changes per unit time at signal lines included in the circuit range to an average value of the number of signal changes per unit time at observing points designated in the circuit range, as a correction coefficient, and a power value-calculating section calculates a power value for each circuit range based on the correction coefficient and the power coefficient calculated for each circuit range.
摘要翻译： 在功率估计器中，功率系数计算部分获取每个电路范围内每单位时间的信号变化次数的平均值，从而计算每个电路范围的功率系数，或者计算每个电路范围的功率系数， 每单位时间的信号变化次数的值等于1，校正系数计算部分计算包括在电路范围中的信号线处的每单位时间的信号变化次数的平均值与平均值的比值 在电路范围中指定的观测点处的每单位时间的信号变化的数量作为校正系数，并且功率值计算部分基于校正系数和为每个电路计算的功率系数来计算每个电路范围的功率值 范围。
-
公开(公告)号：US20070011440A1
公开(公告)日：2007-01-11
申请号：US11358207
申请日：2006-02-22
申请人： Junichi Niitsuma
发明人： Junichi Niitsuma
IPC分类号： G06F9/30
CPC分类号： G06F9/384
摘要： A processor for performing processing based on an instruction code stored in an instruction memory. In the instruction code, a plurality of operations corresponding to a common calculation pattern are represented by a common instruction set designating logical registers. A register-assignment control unit includes a plurality of register-map tables, and determines one or more physical registers assigned to the logical registers designated by the common instruction set, by use of one of the register-map tables which is designated when the common instruction set is called, where each of the register-map tables stores information indicating assignment of one or more physical registers to logical registers.
摘要翻译： 一种处理器，用于基于存储在指令存储器中的指令代码执行处理。 在指令代码中，对应于公共计算模式的多个操作由指定逻辑寄存器的公共指令集表示。 寄存器分配控制单元包括多个寄存器映射表，并且通过使用在公共指令集中指定的寄存器映射表中的一个来确定分配给由公共指令集指定的逻辑寄存器的一个或多个物理寄存器 调用指令集，其中每个寄存器映射表存储指示将一个或多个物理寄存器分配给逻辑寄存器的信息。
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.023 秒)
