公开(公告)号：US20080010533A1

公开(公告)日：2008-01-10

申请号：US11764833

申请日：2007-06-19

申请人： KATSUNORI HIRANO ,  Tadanobu Toba ,  Yuji Sonoda

发明人： KATSUNORI HIRANO ,  Tadanobu Toba ,  Yuji Sonoda

IPC分类号： G06F11/00

CPC分类号： G06F11/26

摘要： In a circuit board on which a plurality of CPUs are mounted, the CPUs comprises: monitor units for outputting task statuses of the respective CPUs; and a diagnosis circuit connected to the plurality of CPUs, comparing and judging combinations of the task statuses of the plurality of CPUs based on information on task statuses outputted from the monitor units, and detecting false operations and failures of the circuit board.

摘要翻译： 在其上安装有多个CPU的电路板中，CPU包括：用于输出各个CPU的任务状态的监视单元; 以及连接到所述多个CPU的诊断电路，基于从所述监视器单元输出的任务状态的信息，比较和判断所述多个CPU的任务状态的组合，以及检测所述电路板的错误操作和故障。