Based device risk assessment
    1.
    发明授权

    公开(公告)号:US10223492B1

    公开(公告)日:2019-03-05

    申请号:US14178866

    申请日:2014-02-12

    IPC分类号: G06F17/50 G06F11/00 H01J37/26

    摘要: The process for design based assessment includes the following steps. First, the process defines multiple patterns of interest (POIs) utilizing design data of a device and then generates a design based classification database. Further, the process receives one or more inspection results. Then, the process compares the inspection results to each of the plurality of POIs in order to identify occurrences of the POIs in the inspection results. In turn, the process determines yield impact of each POI utilizing process yield data and monitors a frequency of occurrence of each of the POIs and the criticality of the POIs in order to identify process excursions of the device. Finally, the process determines a device risk level by calculating a normalized polygon frequency for the device utilizing a frequency of occurrence for each of the critical polygons and a criticality for each of the critical polygons.