公开(公告)号：US20130234765A1

公开(公告)日：2013-09-12

申请号：US13602270

申请日：2012-09-03

Applicant: Kang Seol LEE ,  Jae Hyuk IM

Inventor： Kang Seol LEE ,  Jae Hyuk IM

IPC: H03L5/00

CPC classification number: G11C5/14 ,  G11C5/145 ,  G11C11/4074 ,  H03L5/00

Abstract: A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.

Abstract translation: 半导体存储装置的电压产生电路包括被配置为向输出节点提供电压的多个泵送单元; 感测单元，被配置为感测所述输出节点的电压电平并产生泵送使能信号; 配置为响应于所述泵浦使能信号产生振荡器信号的振荡器; 以及控制单元，被配置为响应于有效信号，上电信号和模式寄存器设置信号而选择性地将振荡器信号输出到多个泵浦单元。

公开(公告)号：US20120105142A1

公开(公告)日：2012-05-03

申请号：US12966706

申请日：2010-12-13

Applicant: Jae Hyuk IM

Inventor： Jae Hyuk IM

IPC: G05F1/10

CPC classification number: G05F1/56 ,  H01C17/22 ,  Y10T307/305

Abstract: A semiconductor apparatus includes: a master chip and at least one slave chip configured to be stacked one on top of another; and a through-silicon via (TSV) configured to penetrate and electrically couple the master chip and the at least one slave chip, wherein the at least one slave chip receives a reference voltage generated from the master chip via the TSV and independently trims the reference voltage and then generates an internal voltage with the trimmed reference voltage.

Abstract translation: 半导体装置包括：主芯片和至少一个从属芯片，其被配置为一个在另一个的顶部上堆叠; 和贯穿硅通孔（TSV），其被配置为穿透并电耦合所述主芯片和所述至少一个从芯片，其中所述至少一个从芯片经由所述TSV接收从所述主芯片产生的参考电压，并且独立地修整所述参考 电压，然后产生具有修整的参考电压的内部电压。

公开(公告)号：US20120249221A1

公开(公告)日：2012-10-04

申请号：US13219636

申请日：2011-08-27

Applicant: Sang Mook OH ,  Jae Hyuk IM

Inventor： Sang Mook OH ,  Jae Hyuk IM

IPC: H01H37/02

CPC classification number: G11C17/16 ,  G11C29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated circuit includes a fuse set; a terminal assigned to be applied with a first external signal in a normal operation; and a control unit configured to receive a second external signal through the terminal and apply the received second external signal to the fuse set in a fuse control operation.

Abstract translation: 半导体集成电路包括保险丝组; 被分配为在正常操作中被施加第一外部信号的终端; 以及控制单元，被配置为通过所述终端接收第二外部信号，并且在所述熔丝控制操作中将所接收的第二外部信号施加到所述熔丝组。