SOI CMOS compatible multiplanar capacitor
    1.
    发明授权
    SOI CMOS compatible multiplanar capacitor 有权
    SOI CMOS兼容多平面电容器

    公开(公告)号:US07728371B2

    公开(公告)日:2010-06-01

    申请号:US11857770

    申请日:2007-09-19

    IPC分类号: H01L27/108

    摘要: An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.

    摘要翻译: 孤立的浅沟槽隔离部分形成在绝缘体上半导体衬底的顶部半导体部分以及浅沟槽隔离结构中。 环形形状的沟槽形成在掺杂顶部半导体部分周围,并填充有诸如掺杂多晶硅的导电材料。 隔离的浅沟槽隔离部分和由导电材料的环限定的掩​​埋绝缘体层的部分被蚀刻以形成空腔。 在空腔内的暴露的半导体表面上和掺杂的顶部半导体部分之上形成电容器电介质。 形成在沟槽中并且在掺杂顶部半导体部分上方的导电材料部分构成电容器的内部电极,而导电材料的环,掺杂的顶部半导体部分和与电容器电介质邻接的手柄衬底的一部分构成一个 第二电极。