Single-end-zero receiver circuit
    1.
    发明授权
    Single-end-zero receiver circuit 失效
    单端接收电路

    公开(公告)号:US06570934B1

    公开(公告)日:2003-05-27

    申请号:US09454913

    申请日:1999-12-06

    申请人: Kanji Harada

    发明人: Kanji Harada

    IPC分类号: H03K900

    摘要: An object of the invention is to prevent an erroneous operation of the internal circuits due to glitches and to dispense with a circuit as a countermeasure against glitches. There are provided a low-value threshold detector, a high-value threshold detector, and a set/reset latch circuit. The low-value threshold detector receives two differential data input DATA+ and DATA− signals and detects whether both input signals are lower than a first threshold voltage. The high-value threshold detector receives the input DATA+ and DATA− signals and detects whether one of the input signals is higher than a second threshold voltage. And the set/reset latch circuit is used for outputting an SE0 signal. the set/reset latch circuit is set when the levels of both input DATA+ and DATA− signals are lower than or equal to the first threshold voltage, and is reset when one of the levels of the input DATA+ and DATA− signals is higher than or equal to the second threshold voltage.

    摘要翻译: 本发明的目的是防止由于毛刺引起的内部电路的错误操作,并且省略了电路作为防止毛刺的对策。 提供了低值阈值检测器,高值阈值检测器和设置/复位锁存电路。 低值阈值检测器接收两个差分数据输入DATA +和DATA-信号,并检测输入信号是否低于第一阈值电压。 高值阈值检测器接收输入的DATA +和DATA-信号,并检测输入信号中的一个是否高于第二阈值电压。 并且设置/复位锁存电路用于输出SE0信号。 当输入DATA +和DATA-信号的电平都低于或等于第一阈值电压时,置位/复位锁存电路被置位,并且当输入DATA +和DATA-信号的一个电平高于或等于第一阈值电压时复位, 等于第二阈值电压。