公开(公告)号：US08190800B2

公开(公告)日：2012-05-29

申请号：US12167533

申请日：2008-07-03

申请人： Katsuyoshi Tanaka ,  Atsushi Kishihara

发明人： Katsuyoshi Tanaka ,  Atsushi Kishihara

IPC分类号： G06F13/00

CPC分类号： G07F9/02

摘要： In a configuration where a main control unit and various peripheral modules are bus-connected on a communication line, the communication line includes a control line in addition to signal lines serving as a differential pair. The control line is, for example, a bus of the logical AND. When the main control unit drives the control line to a ‘L’ level for a certain period of time or more, the peripheral modules detect that and carry out a hardware reset for itself. When the main control unit issues a command to output a value of a particular bit of own identification number to the peripheral modules via the signal lines, the peripheral modules output the result to the control line, and the control line performs an AND operation. By utilizing the AND operation result, automatic address allocation to the peripheral modules is carried out.

摘要翻译： 在主控制单元和各种外围模块在通信线路上总线连接的配置中，除了用作差分对的信号线之外，通信线路还包括控制线。 控制线是例如逻辑与的总线。 当主控制单元将控制线驱动到“L”电平一段时间或更长时间时，外围模块会自动检测并执行硬件复位。 当主控制单元经由信号线向外围模块发出自身识别号码的特定位的值的命令时，外围模块将结果输出到控制线，控制线进行“与”运算。 通过使用AND运算结果，对外围模块进行自动地址分配。

公开(公告)号：US20090012646A1

公开(公告)日：2009-01-08

申请号：US12167533

申请日：2008-07-03

申请人： Katsuyoshi Tanaka ,  Atsushi Kishihara

发明人： Katsuyoshi Tanaka ,  Atsushi Kishihara

IPC分类号： G06F17/00 ,  H04L12/40

CPC分类号： G07F9/02

摘要： In a configuration where a main control unit and various peripheral modules are bus-connected on a communication line, the communication line includes a control line in addition to signal lines serving as a differential pair. The control line is, for example, a bus of the logical AND. When the main control unit drives the control line to a ‘L’ level for a certain period of time or more, the peripheral modules detect that and carry out a hardware reset for itself. When the main control unit issues a command to output a value of a particular bit of own identification number to the peripheral modules via the signal lines, the peripheral modules output the result to the control line, and the control line performs an AND operation. By utilizing the AND operation result, automatic address allocation to the peripheral modules is carried out.

摘要翻译： 在主控制单元和各种外围模块在通信线路上总线连接的配置中，除了用作差分对的信号线之外，通信线路还包括控制线。 控制线是例如逻辑与的总线。 当主控制单元将控制线驱动到“L”电平一段时间或更长时间时，外围模块会自动检测并执行硬件复位。 当主控制单元通过信号线向外围模块发出自己的识别号码的特定位的值的命令时，外围模块将结果输出到控制线，控制线进行“与”运算。 通过使用AND运算结果，对外围模块进行自动地址分配。