公开(公告)号：US5856926A

公开(公告)日：1999-01-05

申请号：US599090

申请日：1996-02-07

申请人： Kazuhiko Matsumoto ,  Takao Shinsha ,  Nobuyuki Hayashi ,  Hiromoto Sakaki ,  Miyako Tandai ,  Yasunori Yamada ,  Takahiro Nakata ,  Kaoru Moriwaki ,  Junji Koshishita

发明人： Kazuhiko Matsumoto ,  Takao Shinsha ,  Nobuyuki Hayashi ,  Hiromoto Sakaki ,  Miyako Tandai ,  Yasunori Yamada ,  Takahiro Nakata ,  Kaoru Moriwaki ,  Junji Koshishita

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： An incremental logic synthesis system for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction. The system includes a logic input device for inputting an old logic, an old circuit generated from the old logic and optimized to satisfy the design constriction, and a new logic partially changing from the old logic file, a logic synthesizing device for generating a first intermediate circuit file from the new logic file, a discriminating device for discriminating a common sub-circuit of the old circuit having an equivalent logic function and an uncommon sub-circuit of the first intermediate circuit having an inconsistent logic function, from the old circuit and the first intermediate circuit, a circuit updating device for generating a second intermediate circuit file by merging the common sub-circuit of the old circuit and the uncommon sub-circuit of the first intermediate circuit, and an optimizing device for optimizing the uncommon sub-circuit of the second intermediate circuit so as to satisfy the design constriction.

摘要翻译： 一种用于从给定逻辑生成优化电路的增量逻辑合成系统，其中所述优化电路满足设计限制。 该系统包括用于输入旧逻辑的逻辑输入装置，从旧逻辑生成并被优化以满足设计限制的旧电路，以及从旧逻辑文件部分改变的新逻辑，用于产生第一中间件的逻辑合成装置 来自新逻辑文件的电路文件，鉴别装置，用于从旧电路和旧电路鉴别具有不一致逻辑功能的第一中间电路的等效逻辑功能和不常用子电路的旧电路的公共子电路， 第一中间电路，用于通过合并旧电路的公共子电路和第一中间电路的不常用子电路来产生第二中间电路文件的电路更新装置，以及用于优化第一中间电路的不常用子电路的优化装置 第二中间电路，以满足设计收缩。

公开(公告)号：US4882690A

公开(公告)日：1989-11-21

申请号：US911461

申请日：1986-09-25

申请人： Takao Shinsha ,  Masato Morita ,  Yoshinori Sakataya ,  Yoji Tsuchiya ,  Mitsuhiro Hikosaka ,  Junji Koshishita ,  Keiho Akiyama ,  Takashige Kubo

发明人： Takao Shinsha ,  Masato Morita ,  Yoshinori Sakataya ,  Yoji Tsuchiya ,  Mitsuhiro Hikosaka ,  Junji Koshishita ,  Keiho Akiyama ,  Takashige Kubo

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A logic design automation system examines correspondence relationship among sublogics in intermediate gate-level logic (containing neither physical design information nor manually optimized logic design information) produced from updated functional-level logic and current gate-level logic (containing the above information) to identify corresponding sublogics and non-corresponding sublogics of the gate-level logics with reference to primary input/output signals and input/output gates. For the corresponding sublogics, the corresponding sublogics of the current gate-level logic are selected, and for the non-corresponding sublogics, the non-corresponding sublogics of the intermediate gate-level logic are selected. The selected sublogics are combined to synthesize updated gate-level logic which preserved therein the physical design information and the manually optimized logic design information for portions of the current gate-level logic which need not be modified.

摘要翻译： 逻辑设计自动化系统检查从更新的功能级逻辑和当前门级逻辑（包含上述信息）产生的中间门级逻辑（不包含物理设计信息或手动优化的逻辑设计信息）的子学习之间的对应关系，以识别 参考主要输入/输出信号和输入/输出门的门级逻辑的相应子语义和非对应子语义。 对于相应的子代码，选择当前门级逻辑的相应子代码，并且对于非对应的子代码，选择中间门级逻辑的非对应子语义。 所选择的子实体被组合以合成更新的门级逻辑，其中保留了不需要修改的当前门级逻辑的部分的物理设计信息和手动优化的逻辑设计信息。