公开(公告)号：US08369713B2

公开(公告)日：2013-02-05

申请号：US12727121

申请日：2010-03-18

申请人： Kazutaka Hara ,  Shunji Kimura ,  Hirotaka Nakamura ,  Koji Kitahara ,  Yoshikazu Urabe ,  Masahiro Endo

发明人： Kazutaka Hara ,  Shunji Kimura ,  Hirotaka Nakamura ,  Koji Kitahara ,  Yoshikazu Urabe ,  Masahiro Endo

IPC分类号： H04B10/00

CPC分类号： H04L25/0262

摘要： In the present invention, unlike a conventional circuit, discrimination is not made by integrating a logical code that includes “0” and “1” to some extent and produced from a random code, but repetition of an identical pattern of a well-known preamble signal added to a head portion of a signal is discriminated when a bit-rate of the signal is changed. More specifically, the repetition of the identical pattern is converted into a consecutive identical signal to generate the consecutive identical signal (having a length of tens bits to thousands bits). Although the consecutive identical signal is longer than a same-code continuation length included in the signal, and is shorter than a time constant necessary to the conventional circuit by about one to three digits. Therefore, an integration time can be shortened to the same degree as the generated consecutive identical signal length, and the bit-rate can be discriminated at high speed within a preamble signal receiving time.

摘要翻译： 在本发明中，与传统电路不同，不是通过将包含0和1的逻辑码在某种程度上进行积分并且由随机码产生，而是将已知的前同步信号的相同模式重复加到 当信号的比特率改变时，鉴别信号的头部。 更具体地，将相同图案的重复转换为连续的相同信号，以产生连续相同的信号（具有十位至数千比特的长度）。 虽然连续相同的信号比包括在信号中的相同代码连续长度更长，并且比常规电路所需的时间常数大约一到三位数。 因此，可以将积分时间缩短到与所生成的连续相同的信号长度相同的程度，并且可以在前导码信号接收时间内以高速判别比特率。

公开(公告)号：US20110229152A1

公开(公告)日：2011-09-22

申请号：US12727121

申请日：2010-03-18

申请人： Kazutaka Hara ,  Shunji Kimura ,  Hirotaka Nakamura ,  Koji Kitahara ,  Yoshikazu Urabe ,  Masahiro Endo

发明人： Kazutaka Hara ,  Shunji Kimura ,  Hirotaka Nakamura ,  Koji Kitahara ,  Yoshikazu Urabe ,  Masahiro Endo

IPC分类号： H04B10/06

CPC分类号： H04L25/0262

摘要： In the present invention, unlike a conventional circuit, discrimination is not made by integrating a logical code that includes “0” and “1” to some extent and produced from a random code, but repetition of an identical pattern of a well-known preamble signal added to a head portion of a signal is discriminated when a bit-rate of the signal is changed. More specifically, the repetition of the identical pattern is converted into a consecutive identical signal to generate the consecutive identical signal (having a length of tens bits to thousands bits). Although the consecutive identical signal is longer than a same-code continuation length included in the signal, and is shorter than a time constant necessary to the conventional circuit by about one to three digits. Therefore, an integration time can be shortened to the same degree as the generated consecutive identical signal length, and the bit-rate can be discriminated at high speed within a preamble signal receiving time.

摘要翻译： 在本发明中，与传统电路不同，不是通过将包含“0”和“1”的逻辑码在某种程度上进行积分而产生的，而是由随机码产生，而是重复公知前导码的相同模式 当信号的比特率改变时，鉴别加到信号头部的信号。 更具体地，将相同图案的重复转换为连续的相同信号，以产生连续相同的信号（具有十位至数千比特的长度）。 虽然连续相同的信号比包括在信号中的相同代码连续长度更长，并且比常规电路所需的时间常数大约一到三位数。 因此，可以将积分时间缩短到与所生成的连续相同的信号长度相同的程度，并且可以在前导码信号接收时间内以高速判别比特率。

公开(公告)号：US08094692B2

公开(公告)日：2012-01-10

申请号：US12867443

申请日：2009-02-20

申请人： Hirotaka Nakamura ,  Shunji Kimura ,  Kazutaka Hara ,  Koji Kitahara

发明人： Hirotaka Nakamura ,  Shunji Kimura ,  Kazutaka Hara ,  Koji Kitahara

IPC分类号： H01S3/10 ,  H01S3/13

CPC分类号： H01S5/042 ,  G02F1/0123 ,  H01S5/0427

摘要： A modulation method according to the invention is applied to a modulation device in which a light source is driven by a differential signal while a modulation circuit and the light source are capacitively coupled. In the modulation method of the invention, when an average potential fluctuates at an input terminal of the light source, a potential fluctuation is externally provided using a control circuit such that a normal phase side and a reverse phase side become equal to each other in a time constant of the fluctuation in average potential, and transient states of the average potentials at the normal phase side and reverse phase side are equalized and cancel each other as in-phase components of a signal input to the light source, which allows an optical signal to be normally transmitted from the light source. The optical signal can normally be transmitted from the light source even before the average potentials at a normal phase input terminal and a reverse phase input terminal of the light source are stabilized.

摘要翻译： 根据本发明的调制方法被应用于其中调制电路和光源电容耦合时由差分信号驱动光源的调制装置。 在本发明的调制方法中，当平均电位在光源的输入端波动时，使用控制电路外部提供电位波动，使得正常相位侧和反相侧在 平均电位的波动的时间常数以及正相侧和反相侧的平均电位的过渡状态被均衡并相互抵消，作为输入到光源的信号的同相分量，这允许光信号 从光源正常传输。 即使在光源的正相输入端子和反相输入端子的平均电位稳定之前，也可以从光源发送光信号。

公开(公告)号：US20110033193A1

公开(公告)日：2011-02-10

申请号：US12867443

申请日：2009-02-20

申请人： Hirotaka Nakamura ,  Shunji Kimura ,  Kazutaka Hara ,  Koji Kitahara

发明人： Hirotaka Nakamura ,  Shunji Kimura ,  Kazutaka Hara ,  Koji Kitahara

IPC分类号： H04B10/04 ,  H03C1/36

CPC分类号： H01S5/042 ,  G02F1/0123 ,  H01S5/0427

摘要： A modulation method according to the invention is applied to a modulation device in which a light source is driven by a differential signal while a modulation circuit and the light source are capacitively coupled. In the modulation method of the invention, when an average potential fluctuates at an input terminal of the light source, a potential fluctuation is externally provided using a control circuit such that a normal phase side and a reverse phase side become equal to each other in a time constant of the fluctuation in average potential, and transient states of the average potentials at the normal phase side and reverse phase side are equalized and cancel each other as in-phase components of a signal input to the light source, which allows an optical signal to be normally transmitted from the light source. The optical signal can normally be transmitted from the light source even before the average potentials at a normal phase input terminal and a reverse phase input terminal of the light source are stabilized.

摘要翻译： 根据本发明的调制方法被应用于其中调制电路和光源电容耦合时由差分信号驱动光源的调制装置。 在本发明的调制方法中，当平均电位在光源的输入端波动时，使用控制电路外部提供电位波动，使得正常相位侧和反相侧在 平均电位的波动的时间常数以及正相侧和反相侧的平均电位的过渡状态被均衡并相互抵消，作为输入到光源的信号的同相分量，这允许光信号 从光源正常传输。 即使在光源的正相输入端子和反相输入端子的平均电位稳定之前，也可以从光源发送光信号。

公开(公告)号：US20060268969A1

公开(公告)日：2006-11-30

申请号：US10543656

申请日：2005-02-16

申请人： Shunji Kimura ,  Tomoaki Yoshida ,  Koji Kitahara ,  Hiroshi Takada

发明人： Shunji Kimura ,  Tomoaki Yoshida ,  Koji Kitahara ,  Hiroshi Takada

IPC分类号： H04B17/00

CPC分类号： H04B10/6931 ,  H03F3/087 ,  H03G3/3084 ,  H04L25/0262

摘要： A bit-rate automatic control circuit for feedback controlling the gain and bandwidth of a preamplifier in dependence on the bit-rate of a signal is disclosed. The circuit includes a bit-rate discrimination circuit configured to discriminate the bit rate of the signal, and an alarm circuit configured to determine whether the value of received power of the signal is less than the minimum acceptable value of the preamplifier or not. If said alarm circuit determines that the value of received power of the signal is less than the minimum acceptable value of the preamplifier, the bit-rate automatic control circuit determines, irrespective of the discrimination of said bit-rate discrimination circuit, that the bit-rate of the signal is low, and feedback controls the preamplifier based on the determination. According to the above arrangements, if a determination is made that the reception level of the input signal is lower than the minimum acceptable value of received power, the preamplifier can be switched from a state for receiving a high bit-rate signal to a state for receiving a low bit-rate signal.

摘要翻译： 公开了一种用于根据信号比特率反馈控制前置放大器的增益和带宽的比特率自动控制电路。 电路包括：比特率鉴别电路，被配置为鉴别信号的比特率;以及报警电路，被配置为确定信号的接收功率的值是否小于前置放大器的最小可接受值。 如果所述报警电路确定信号的接收功率的值小于前置放大器的最小可接受值，则比特率自动控制电路确定与所述比特率鉴别电路的鉴别无关， 信号速率低，反馈控制前置放大器基于该判定。 根据上述配置，如果确定输入信号的接收电平低于接收功率的最小可接受值，则可以从用于接收高比特率信号的状态切换到前置放大器的状态 接收低比特率信号。

公开(公告)号：US20060159163A1

公开(公告)日：2006-07-20

申请号：US10546424

申请日：2005-02-16

申请人： Shunji Kimura ,  Tomoaki Yoshida ,  Koji Kitahara ,  Hiroshi Takada

发明人： Shunji Kimura ,  Tomoaki Yoshida ,  Koji Kitahara ,  Hiroshi Takada

IPC分类号： H04B17/00

CPC分类号： H03K5/086 ,  H04L25/0262

摘要： A bit-rate discrimination circuit for determining which bit-rate an input signal has, a first bit-rate or a second bit-rate higher than the first bit-rate, is disclosed. The circuit is characterized by a frequency selection unit configured to filter out a signal having the second bit-rate, and allow at least a fraction of the low frequency component of a signal having the first bit-rate to pass through; a determination unit configured to determine whether the fraction of the low frequency component of the signal having the first bit-rate has passed through said frequency selection unit; a smoothing unit configured to smooth the output of said determination unit; and a level conversion unit configured to convert the output of said smoothing unit to a logic level. According to the above arrangements, the bit-rate of the input signal can be discriminated based on the low frequency component thereof.

摘要翻译： 一种比特率鉴别电路，用于确定输入信号具有哪个比特率，比第一比特率高的第一比特率或第二比特率。 该电路的特征在于，频率选择单元被配置为滤除具有第二比特率的信号，并且允许具有第一比特率的信号的低频分量的至少一部分通过; 确定单元，被配置为确定具有第一比特率的信号的低频分量的分数是否已经通过所述频率选择单元; 平滑单元，被配置为平滑所述确定单元的输出; 以及电平转换单元，被配置为将所述平滑单元的输出转换为逻辑电平。 根据上述配置，可以基于其低频分量来区分输入信号的比特率。

公开(公告)号：US07936842B2

公开(公告)日：2011-05-03

申请号：US10543656

申请日：2005-02-16

申请人： Shunji Kimura ,  Tomoaki Yoshida ,  Koji Kitahara ,  Hiroshi Takada

发明人： Shunji Kimura ,  Tomoaki Yoshida ,  Koji Kitahara ,  Hiroshi Takada

IPC分类号： H04L27/08

CPC分类号： H04B10/6931 ,  H03F3/087 ,  H03G3/3084 ,  H04L25/0262

摘要： A bit-rate automatic control circuit for feedback controlling the gain and bandwidth of a preamplifier in dependence on the bit-rate of a signal is disclosed. The circuit includes a bit-rate discrimination circuit configured to discriminate the bit rate of the signal, and an alarm circuit configured to determine whether the value of received power of the signal is less than the minimum acceptable value of the preamplifier or not. If said alarm circuit determines that the value of received power of the signal is less than the minimum acceptable value of the preamplifier, the bit-rate automatic control circuit determines, irrespective of the discrimination of said bit-rate discrimination circuit, that the bit-rate of the signal is low, and feedback controls the preamplifier based on the determination. According to the above arrangements, if a determination is made that the reception level of the input signal is lower than the minimum acceptable value of received power, the preamplifier can be switched from a state for receiving a high bit-rate signal to a state for receiving a low bit-rate signal.

摘要翻译： 公开了一种用于根据信号比特率反馈控制前置放大器的增益和带宽的比特率自动控制电路。 电路包括：比特率鉴别电路，被配置为鉴别信号的比特率;以及报警电路，被配置为确定信号的接收功率的值是否小于前置放大器的最小可接受值。 如果所述报警电路确定信号的接收功率的值小于前置放大器的最小可接受值，则比特率自动控制电路确定与所述比特率鉴别电路的鉴别无关， 信号速率低，反馈控制前置放大器基于该判定。 根据上述配置，如果确定输入信号的接收电平低于接收功率的最小可接受值，则可以从用于接收高比特率信号的状态切换到前置放大器的状态 接收低比特率信号。

公开(公告)号：US07881414B2

公开(公告)日：2011-02-01

申请号：US10546424

申请日：2005-02-16

申请人： Shunji Kimura ,  Tomoaki Yoshida ,  Koji Kitahara ,  Hiroshi Takada

发明人： Shunji Kimura ,  Tomoaki Yoshida ,  Koji Kitahara ,  Hiroshi Takada

IPC分类号： H04B17/00

CPC分类号： H03K5/086 ,  H04L25/0262

摘要： A bit-rate discrimination circuit for determining which bit-rate an input signal has, a first bit-rate or a second bit-rate higher than the first bit-rate, is disclosed. The circuit is characterized by a frequency selection unit configured to filter out a signal having the second bit-rate, and allow at least a fraction of the low frequency component of a signal having the first bit-rate to pass through; a determination unit configured to determine whether the fraction of the low frequency component of the signal having the first bit-rate has passed through said frequency selection unit; a smoothing unit configured to smooth the output of said determination unit; and a level conversion unit configured to convert the output of said smoothing unit to a logic level. According to the above arrangements, the bit-rate of the input signal can be discriminated based on the low frequency component thereof.

摘要翻译： 一种比特率鉴别电路，用于确定输入信号具有哪个比特率，比第一比特率高的第一比特率或第二比特率。 该电路的特征在于，频率选择单元被配置为滤除具有第二比特率的信号，并且允许具有第一比特率的信号的低频分量的至少一部分通过; 确定单元，被配置为确定具有第一比特率的信号的低频分量的分数是否已经通过所述频率选择单元; 平滑单元，被配置为平滑所述确定单元的输出; 以及电平转换单元，被配置为将所述平滑单元的输出转换为逻辑电平。 根据上述配置，可以基于其低频分量来区分输入信号的比特率。

公开(公告)号：US20110170832A1

公开(公告)日：2011-07-14

申请号：US12983984

申请日：2011-01-04

申请人： Sawako Yamai ,  Susumu Okabe ,  Tsuyoshi Ito ,  Kota Asaka ,  Koji Kitahara ,  Toshio Ishikawa

发明人： Sawako Yamai ,  Susumu Okabe ,  Tsuyoshi Ito ,  Kota Asaka ,  Koji Kitahara ,  Toshio Ishikawa

IPC分类号： G02B6/36 ,  B23P11/00

CPC分类号： G02B6/4246 ,  G02B6/4201 ,  G02B6/4261 ,  G02B6/428 ,  G02B6/4281 ,  G02B6/4283 ,  G02B6/4285 ,  Y10T29/49826

摘要： An optical transceiver module that is capable of being inserted into and removed from a cage includes a housing that houses a photoelectric conversion element, the housing having a guiding section formed along a front-rear direction, an operating lever that has an operating section and a lever-side contact section, the operating lever being attached to the housing in a rotatable manner about an axis of rotation; and a slider that has a wedge section that engages with a latching section provided to the cage, and a slider-side contact section that comes into contact with the lever-side contact section, the slider being guided in the front-rear direction by the guiding section, the lever-side contact section being located opposite the operating section with respect to the axis of rotation, and as the operating section is pushed rearward, the lever-side contact section pushes the slider-side contact section forward and the slider moves forward to a position where the wedge section is unlatched from the latching section.

摘要翻译： 能够插入到笼中并从笼中移除的光收发器模块包括容纳光电转换元件的壳体，壳体具有沿前后方向形成的引导部分，操作杆具有操作部分和 杠杆侧接触部分，操作杆以围绕旋转轴线的可旋转方式附接到壳体; 以及滑块，其具有与设置在所述保持架上的闩锁部分接合的楔形部分，以及与所述杠杆侧接触部分接触的滑块侧接触部分，所述滑块在前后方向上被引导 引导部，所述杆侧接触部相对于所述旋转轴线位于所述操作部的相对侧，并且当所述操作部被向后推时，所述杆侧接触部将所述滑块侧接触部向前方推动，并且所述滑块移动 前进到楔形部分从闩锁部分解锁的位置。

公开(公告)号：US09447267B2

公开(公告)日：2016-09-20

申请号：US13992566

申请日：2011-12-07

申请人： Hironori Matsumoto ,  Hirotaka Uosaki ,  Koji Kitahara ,  Yuji Sawada

发明人： Hironori Matsumoto ,  Hirotaka Uosaki ,  Koji Kitahara ,  Yuji Sawada

IPC分类号： B32B27/32 ,  C08L23/12 ,  B32B27/08 ,  C08L23/10 ,  C08L23/14 ,  C08L23/08

CPC分类号： C08L23/12 ,  B32B27/08 ,  B32B27/32 ,  B32B27/327 ,  B32B2250/246 ,  B32B2307/7244 ,  B32B2439/70 ,  C08L23/0815 ,  C08L23/10 ,  C08L23/14 ,  C08L2205/02 ,  Y10T428/3192 ,  Y10T428/31938

摘要： It is an object of the present invention to provide a modified polypropylene composition for forming laminates, which enables prevention of lowering of interlaminar bond strength even in the case where it is subjected to high-speed molding or subjected to stretch molding, and a laminate using the composition and having excellent interlaminar bond properties. The present invention relates to a modified polypropylene composition comprising a propylene-based polymer (A-1), 0 to 45% by weight of a propylene-based polymer (A-2), an ethylene/α-olefin copolymer (B) having a melt flow rate (MFR; ASTM D1238, 230° C., load of 2.16 kg) of 0.01 to 40 g/10 min and a density (ASTM D1505) of not more than 0.900 g/cm3, and a specific amount of modified polypropylene (C) a part or all of which has been graft-modified with an unsaturated carboxylic acid or a derivative thereof.

摘要翻译： 本发明的目的是提供一种用于形成层压体的改性聚丙烯组合物，即使在经受高速成型或拉伸成型的情况下也能够防止层间粘合强度降低，并且使用 该组合物具有优异的层间粘合性能。 本发明涉及包含丙烯类聚合物（A-1），0〜45％（重量）丙烯类聚合物（A-2），乙烯·α-烯烃共聚物（B） 熔体流动速率（MFR; ASTM D1238,230℃，负荷2.16kg）为0.01〜40g / 10min，密度（ASTM D1505）为0.900g / cm 3以下，特定量的改性 聚丙烯（C）的一部分或全部已经用不饱和羧酸或其衍生物进行了接枝改性。