公开(公告)号：US07237209B2

公开(公告)日：2007-06-26

申请号：US10819354

申请日：2004-04-07

申请人： Keith R. Strickland ,  Stephen R. Chadfield ,  John B. O'Connell

发明人： Keith R. Strickland ,  Stephen R. Chadfield ,  John B. O'Connell

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method of testing an integrated circuit design to determine whether or not the design satisfies an electrostatic discharge protection specification, said circuit design incorporating electrostatic discharge protection routes between top-level nodes of the design. The method comprises defining an electrostatic discharge protection score for each of said electrostatic discharge protection routes, for each top-level node pair, calculating an electrostatic discharge score for every route through the active circuit between the top-level nodes, and identifying active circuit routes between top-level node pairs for which the electrostatic discharge score is less than the electrostatic discharge protection score for the corresponding electrostatic discharge protection route, or lies within a predefined amount of that score.

摘要翻译： 一种测试集成电路设计以确定设计是否满足静电放电保护规范的方法，所述电路设计在设计的顶级节点之间并入静电放电保护路线。 该方法包括为每个顶级节点对为每个所述静电放电保护路径定义静电放电保护得分，计算通过顶级节点之间的有源电路的每条路线的静电放电分数，以及识别有源电路路径 在静电放电得分小于相应的静电放电保护路线的静电放电保护得分的顶级节点对之间，或者处于该分数的预定量内。