公开(公告)号：US4750177A

公开(公告)日：1988-06-07

申请号：US904827

申请日：1986-09-08

申请人： Gardner C. Hendrie ,  Kurt F. Baty ,  Ronald E. Dynneson ,  Daniel M. Falkoff ,  Robert Reid ,  Joseph E. Samson ,  Kenneth T. Wolff

发明人： Gardner C. Hendrie ,  Kurt F. Baty ,  Ronald E. Dynneson ,  Daniel M. Falkoff ,  Robert Reid ,  Joseph E. Samson ,  Kenneth T. Wolff

IPC分类号： G06F11/00 ,  G06F1/04 ,  G06F3/00 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/22 ,  G06F13/00

CPC分类号： G06F11/1625 ,  G06F11/1402 ,  G06F11/1604 ,  G06F11/2005 ,  G06F11/2007 ,  G06F11/2017 ,  G06F11/22 ,  G06F1/04 ,  G06F11/1629 ,  G06F11/1666 ,  G06F11/20

摘要： A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

摘要翻译： 容错计算机系统在计算模块的单元之间提供在所有单元共同的总线结构上的信息传输，包括处理器单元和存储器单元以及一个或多个外围控制单元。 在总线结构和每个单元中，系统的信息处理部分可以具有重复的伙伴。 错误检测器检查总线结构和每个系统单元的操作，仅在无故障总线导体和无故障单元之间提供信息传输。 计算机系统可以通过仅使用无故障的导体和功能单元在基本上不发生故障的情况下以这种方式操作。 具有异常速度和简单性的仲裁电路提供计算模块的单元根据每个单元的优先级访问公共总线结构。 模块的单元检查输入和输出信号是否有错误，向其他模块单元发出检测到的错误信号，并禁止单元向总线结构发送潜在的错误信息。

公开(公告)号：US4486826A

公开(公告)日：1984-12-04

申请号：US307524

申请日：1981-10-01

申请人： Kenneth T. Wolff ,  Joseph E. Samson ,  Kurt F. Baty

发明人： Kenneth T. Wolff ,  Joseph E. Samson ,  Kurt F. Baty

IPC分类号： G06F11/18 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F13/00 ,  G06F13/374 ,  G06F15/16 ,  G06F15/06

CPC分类号： G06F11/1625 ,  G06F11/1641 ,  G06F11/2007 ,  G06F13/374 ,  G06F11/10 ,  G06F11/20

摘要： A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

摘要翻译： 容错计算机系统在计算模块的单元之间提供在所有单元共同的总线结构上的信息传输，包括处理器单元和存储器单元以及一个或多个外围控制单元。 在总线结构和每个单元中，系统的信息处理部分可以具有重复的伙伴。 错误检测器检查总线结构和每个系统单元的操作，仅在无故障总线导体和无故障单元之间提供信息传输。 计算机系统可以通过仅使用无故障的导体和功能单元在基本上不发生故障的情况下以这种方式操作。 具有异常速度和简单性的仲裁电路提供计算模块的单元根据每个单元的优先级访问公共总线结构。 模块的单元检查输入和输出信号是否有错误，向其他模块单元发出检测到的错误信号，并禁止单元向总线结构发送潜在的错误信息。

公开(公告)号：US4654857A

公开(公告)日：1987-03-31

申请号：US762039

申请日：1985-08-02

申请人： Joseph E. Samson ,  Kenneth T. Wolff ,  Robert Reid ,  Gardner C. Hendrie ,  Daniel M. Falkoff ,  Ronald E. Dynneson ,  Daniel M. Clemson ,  Kurt F. Baty

发明人： Joseph E. Samson ,  Kenneth T. Wolff ,  Robert Reid ,  Gardner C. Hendrie ,  Daniel M. Falkoff ,  Ronald E. Dynneson ,  Daniel M. Clemson ,  Kurt F. Baty

IPC分类号： G06F11/18 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F13/00 ,  G06F13/374

CPC分类号： G06F11/1625 ,  G06F11/1641 ,  G06F11/2007 ,  G06F13/374 ,  G06F11/10 ,  G06F11/20

摘要： A fualt-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

摘要翻译： 容错计算机系统在计算模块的单元之间提供在所有单元共同的总线结构上的信息传输，包括处理器单元和存储器单元以及一个或多个外围控制单元。 在总线结构和每个单元中，系统的信息处理部分可以具有重复的伙伴。 错误检测器检查总线结构和每个系统单元的操作，仅在无故障总线导体和无故障单元之间提供信息传输。 计算机系统可以通过仅使用无故障的导体和功能单元在基本上不发生故障的情况下以这种方式操作。 具有异常速度和简单性的仲裁电路提供计算模块的单元根据每个单元的优先级访问公共总线结构。 模块的单元检查输入和输出信号是否有错误，向其他模块单元发出检测到的错误信号，并禁止单元向总线结构发送潜在的错误信息。

公开(公告)号：US4403282A

公开(公告)日：1983-09-06

申请号：US144884

申请日：1980-04-29

申请人： Kenneth D. Holberger ,  Joseph E. Samson

发明人： Kenneth D. Holberger ,  Joseph E. Samson

IPC分类号： G06F11/10 ,  G06F12/02 ,  G06F12/10 ,  G06F13/10 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F11/10 ,  G06F12/0292 ,  G06F13/10 ,  G06F13/28 ,  G06F12/1081

摘要： A data processing system having a central processor unit (CPU) and a memory and further including a high speed, or "burst multiplexer", channel for permitting direct access to the memory by an input/output (I/O) device without the need to use registers and control signals from the central processor unit. The high speed channel utilizes its own memory port separate from that of the CPU and includes internal paths for transferring addresses and data between an I/O device and the memory. The channel further includes a memory allocation unit (MAP) which can be loaded by transfer of memory allocation data via substantially the same common path as the I/O data transfer. Appropriate control logic is also included to control the data and address transfers and the MAP load and dump operations so that blocks of data words can be transferred sequentially and directly to or from the memory.

摘要翻译： 一种具有中央处理器单元（CPU）和存储器并且还包括用于允许输入/输出（I / O）设备直接访问存储器而不需要的高速或“突发多路复用器”通道的数据处理系统 使用来自中央处理器单元的寄存器和控制信号。 高速通道利用其独立于CPU的存储器端口，并且包括用于在I / O设备和存储器之间传送地址和数据的内部路径。 信道还包括存储器分配单元（MAP），其可以通过与I / O数据传输基本相同的公共路径传送存储器分配数据来加载。 还包括适当的控制逻辑以控制数据和地址传送以及MAP加载和转储操作，以便数据字块可以顺序地和直接地从存储器传送。