公开(公告)号：US07007135B2

公开(公告)日：2006-02-28

申请号：US10094261

申请日：2002-03-08

申请人： Keong-Hoon Koo ,  Jin-Cheon Kim

发明人： Keong-Hoon Koo ,  Jin-Cheon Kim

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/12

摘要： A multi-level cache system includes a primary cache and a secondary cache that is accessed by a processor later than the primary cache. If the secondary cache is full with data when the processor misses the access to the primary and secondary cache memories, data stored in the secondary cache must be routed to a main memory. In this case, to satisfy the inclusion property of cache, the data migrating to the main memory from the secondary cache is present in the secondary cache, not in the primary cache. The multi-level cache system does not need to access the primary cache to select the data in the secondary cache but not in the primary cache. Thus, it simplifies a logical composition for controlling the miss/replacement, and shortens an operation time therein.

摘要翻译： 多级缓存系统包括主缓存和次高速缓存，其由处理器在主缓存器之后访问。 如果二级缓存在处理器无法访问主缓存和二级高速缓冲存储器时遇到数据，则存储在二级高速缓存中的数据必须路由到主存储器。 在这种情况下，为了满足高速缓存的包含性质，从辅助高速缓存迁移到主存储器的数据不存在于主缓存中。 多级缓存系统不需要访问主缓存来选择二级缓存中的数据，但不在主缓存中。 因此，它简化了用于控制未命中/替换的逻辑组合，并缩短了其中的操作时间。