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1.发明授权Circuit and method of driving bitlines of integrated circuit memory using improved precharge scheme and sense-amplification scheme 失效使用改进的预充电方案和感测放大方案驱动集成电路存储器的位线的电路和方法公开(公告)号：US07209399B2
公开(公告)日：2007-04-24
申请号：US11180832
申请日：2005-07-13
申请人： Ki-chul Chun , Chang-ho Shin
发明人： Ki-chul Chun , Chang-ho Shin
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C7/12
摘要： Provided are a bitline driving circuit of an integrated circuit memory that enhances a precharge scheme and a sense amplification scheme and a bitline driving method. In the bitline driving circuit, a new scheme of precharging the bitlines to voltages greater than or smaller than a voltage VCCA/2 using an auxiliary circuit is used to increase a gate-source voltage of transistors included in each sense amplification circuit. Also, when cell data is 1 and 0, a dummy cell can maintain a voltage difference between the bitlines BL and BLB generated after charge sharing. Furthermore, a sense amplification circuit, which is controlled by an offset control circuit, can remove a threshold voltage offset between the transistors included in each sense amplification circuit. At this time, an auxiliary circuit is used to stabilize the voltage difference.
摘要翻译： 提供了集成电路存储器的位线驱动电路，其增强了预充电方案和感测放大方案和位线驱动方法。 在位线驱动电路中，使用使用辅助电路将位线预充电至大于或小于电压VCCA / 2的电压的新方案用于增加每个读出放大电路中包括的晶体管的栅极 - 源极电压。 此外，当单元数据为1和0时，虚设单元可以维持电荷共享后产生的位线BL和BLB之间的电压差。 此外，由偏移控制电路控制的感测放大电路可以去除每个感测放大电路中包括的晶体管之间的阈值电压偏移。 此时，使用辅助电路来稳定电压差。
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2.发明申请Circuit and method of driving bitlines of integrated circuit memory using improved precharge scheme and sense-amplification scheme 失效使用改进的预充电方案和感测放大方案驱动集成电路存储器的位线的电路和方法公开(公告)号：US20060023535A1
公开(公告)日：2006-02-02
申请号：US11180832
申请日：2005-07-13
申请人： Ki-chul Chun , Chang-ho Shin
发明人： Ki-chul Chun , Chang-ho Shin
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C7/12
摘要： Provided are a bitline driving circuit of an integrated circuit memory that enhances a precharge scheme and a sense amplification scheme and a bitline driving method. In the bitline driving circuit, a new scheme of precharging the bitlines to voltages greater than or smaller than a voltage VCCA/2 using an auxiliary circuit is used to increase a gate-source voltage of transistors included in each sense amplification circuit. Also, when cell data is 1 and 0, a dummy cell can maintain a voltage difference between the bitlines BL and BLB generated after charge sharing. Furthermore, a sense amplification circuit, which is controlled by an offset control circuit, can remove a threshold voltage offset between the transistors included in each sense amplification circuit. At this time, an auxiliary circuit is used to stabilize the voltage difference.
摘要翻译： 提供了集成电路存储器的位线驱动电路，其增强了预充电方案和感测放大方案和位线驱动方法。 在位线驱动电路中，使用使用辅助电路将位线预充电至大于或小于电压VCCA / 2的电压的新方案用于增加每个读出放大电路中包括的晶体管的栅极 - 源极电压。 此外，当单元数据为1和0时，虚设单元可以维持电荷共享后产生的位线BL和BLB之间的电压差。 此外，由偏移控制电路控制的感测放大电路可以去除每个感测放大电路中包括的晶体管之间的阈值电压偏移。 此时，使用辅助电路来稳定电压差。
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3.发明申请Method of operating semiconductor memory device, semiconductor memory device and portable media system including the same 有权操作半导体存储器件，半导体存储器件和包含该半导体存储器件的便携式介质系统的方法公开(公告)号：US20080159049A1
公开(公告)日：2008-07-03
申请号：US12003561
申请日：2007-12-28
申请人： Young-sun Min , Chang-ho Shin
发明人： Young-sun Min , Chang-ho Shin
IPC分类号： G11C5/14
摘要： A method of operating a semiconductor memory device may include initializing a first internal circuit in response to a first initialization signal based on an internal power voltage. The first initialization signal may be generated if the semiconductor memory device performs a power-up operation. The semiconductor memory device may enter a deep-power-down (DPD) mode without generating the first initialization signal. The first initialization signal may be generated if the semiconductor memory device exits the DPD mode.
摘要翻译： 操作半导体存储器件的方法可以包括基于内部电源电压来响应于第一初始化信号初始化第一内部电路。 如果半导体存储器件执行上电操作，则可以产生第一初始化信号。 半导体存储器件可以进入深度掉电（DPD）模式而不产生第一初始化信号。 如果半导体存储器件退出DPD模式，则可以产生第一初始化信号。
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4.发明授权Method of operating semiconductor memory device, semiconductor memory device and portable media system including the same 有权操作半导体存储器件，半导体存储器件和包含该半导体存储器件的便携式介质系统的方法公开(公告)号：US07800972B2
公开(公告)日：2010-09-21
申请号：US12003561
申请日：2007-12-28
申请人： Young-sun Min , Chang-ho Shin
发明人： Young-sun Min , Chang-ho Shin
IPC分类号： G11C7/00
摘要： A method of operating a semiconductor memory device may include initializing a first internal circuit in response to a first initialization signal based on an internal power voltage. The first initialization signal may be generated if the semiconductor memory device performs a power-up operation. The semiconductor memory device may enter a deep-power-down (DPD) mode without generating the first initialization signal. The first initialization signal may be generated if the semiconductor memory device exits the DPD mode.
摘要翻译： 操作半导体存储器件的方法可以包括基于内部电源电压来响应于第一初始化信号初始化第一内部电路。 如果半导体存储器件执行上电操作，则可以产生第一初始化信号。 半导体存储器件可以进入深度掉电（DPD）模式而不产生第一初始化信号。 如果半导体存储器件退出DPD模式，则可以产生第一初始化信号。
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