公开(公告)号：US20230385462A1

公开(公告)日：2023-11-30

申请号：US18168211

申请日：2023-02-13

Applicant: Kioxia Corporation

Inventor： Kohei OKUDA ,  Hayato FUJIWARA ,  Tatsuya HOSOKAWA ,  Hiroyasu NAKATSUKA ,  Ge WANG

IPC: G06F21/81

CPC classification number: G06F21/81

Abstract: A memory system includes a first controller, a nonvolatile memory connected to the first controller, and a power supply circuit that applies a voltage to the first controller and the nonvolatile memory. The first controller writes first data to a first address in the nonvolatile memory and instructs the power supply circuit to apply the destruction voltage to the nonvolatile memory. The first controller determines whether the first data can be correctly read from the first address in the nonvolatile memory and checks destruction of the nonvolatile memory based on the determination.

公开(公告)号：US20240248797A1

公开(公告)日：2024-07-25

申请号：US18207932

申请日：2023-06-09

Applicant: Kioxia Corporation

Inventor： Hiroyasu NAKATSUKA ,  Koichi NAGAI

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1076 ,  G06F11/0787

Abstract: According to one embodiment, an information processing system includes a host and memory systems. A first memory system stores first data in a nonvolatile memory. A second memory system stores second data in a nonvolatile memory. The host transmits first update data to the first memory system and transmits second update data to the second memory system. The first memory system generates first XOR data by performing an XOR operation on at least the first data and the first update data, and transmits the first XOR data to the second memory system. The second memory system generates second XOR data by performing an XOR operation on the second data, the second update data, and the first XOR data, and transmits the second XOR data to a third memory system.