公开(公告)号：US20220406363A1

公开(公告)日：2022-12-22

申请号：US17549262

申请日：2021-12-13

Applicant: Kioxia Corporation

Inventor： Mutsumi OKAJIMA ,  Mamoru ISHIZAKA

IPC: G11C11/4091 ,  G11C5/02 ,  H01L23/48

Abstract: A semiconductor memory device includes: memory units arranged in a first direction; first semiconductor layers arranged in the first direction and electrically connected to the memory units; first gate electrodes arranged in the first direction and opposed to the first semiconductor layers; a first wiring extending in the first direction and connected to the first semiconductor layers; second wirings arranged in the first direction, and connected to the first gate electrodes; second semiconductor layers arranged in the first direction and disposed at first end portions of the second wirings; second gate electrodes arranged in the first direction and opposed to the second semiconductor layers; third semiconductor layers arranged in the first direction and disposed at second end portions of the second wirings; and third gate electrodes arranged in the first direction and opposed to the third semiconductor layers.

公开(公告)号：US20250022530A1

公开(公告)日：2025-01-16

申请号：US18768033

申请日：2024-07-10

Applicant: Kioxia Corporation

Inventor： Takeshi AOKI ,  Masaharu WADA ,  Mamoru ISHIZAKA

IPC: G11C29/44

Abstract: A memory device includes memory cells, first wirings extending along a first direction and connected to the cells, second wirings extending along a second direction and connected to the cells, the second direction intersecting the first direction, third wirings extending along a third direction and each connected to one or more second wirings, the third direction intersecting the first and second directions, sense circuits each connected to one or more third wirings, a switching circuit connected to the circuits and selectively outputting signals from the sense circuits, and a control circuit storing first addresses indicating second and third wirings connected to defective cells, and when a memory cell is selected, determining second addresses indicating second and third wirings connected to the selected cell, and based on the first and second addresses, controlling the switching circuit not to output signals from one or more sense circuits connected to the defective cells.

公开(公告)号：US20230200051A1

公开(公告)日：2023-06-22

申请号：US17841529

申请日：2022-06-15

Applicant: Kioxia Corporation

Inventor： Takeshi AOKI ,  Masaharu WADA ,  Mamoru ISHIZAKA ,  Tsuneo INABA

IPC: H01L27/108 ,  G11C11/4091 ,  H01L29/786

CPC classification number: H01L27/10805 ,  H01L27/10897 ,  G11C11/4091 ,  H01L29/7869

Abstract: A semiconductor memory device comprises a memory cell array. The memory cell array comprises sub arrays. The sub array comprises: memory portions; first semiconductor layers electrically connected to memory portions; first gate electrodes respectively facing first semiconductor layers; a first wiring electrically connected to first semiconductor layers; second wirings connected to first gate electrodes; second semiconductor layers electrically connected to first end portions of second wirings; second gate electrodes facing second semiconductor layers; and a third wiring electrically connected to second semiconductor layers. The memory cell array comprises fourth wirings that extend in one direction across the sub arrays and are connected to second gate electrodes.