METHOD AND SYSTEM FOR BUFFER ALLOCATION MANAGEMENT FOR A MEMORY DEVICE

    公开(公告)号:US20230047029A1

    公开(公告)日:2023-02-16

    申请号:US17402192

    申请日:2021-08-13

    Abstract: Example implementations include a non-transitory processor-readable media comprising processor-readable instructions that when executed by at least one processor of a controller, causes the processor to generate at least one memory address corresponding respectively to at least one command block, the command block being associated with a command to a memory device, allocate the memory address to a buffer addressing unit associated with a host interface, the memory address including a buffer memory identifier associated with a buffer memory block and a buffer memory address associated with the buffer memory block, and update a request count associated with the buffer memory block by incrementing a reference counter associated with the buffer memory block.

    Method and system for buffer allocation management for a memory device

    公开(公告)号:US12118235B2

    公开(公告)日:2024-10-15

    申请号:US17402192

    申请日:2021-08-13

    Abstract: Example implementations include a non-transitory processor-readable media comprising processor-readable instructions that when executed by at least one processor of a controller, causes the processor to generate at least one memory address corresponding respectively to at least one command block, the command block being associated with a command to a memory device, allocate the memory address to a buffer addressing unit associated with a host interface, the memory address including a buffer memory identifier associated with a buffer memory block and a buffer memory address associated with the buffer memory block, and update a request count associated with the buffer memory block by incrementing a reference counter associated with the buffer memory block.

    METHOD AND SYSTEM FOR BUFFER ALLOCATION MANAGEMENT FOR A MEMORY DEVICE

    公开(公告)号:US20250036311A1

    公开(公告)日:2025-01-30

    申请号:US18915048

    申请日:2024-10-14

    Abstract: Example implementations include a non-transitory processor-readable media comprising processor-readable instructions that when executed by at least one processor of a controller, causes the processor to generate at least one memory address corresponding respectively to at least one command block, the command block being associated with a command to a memory device, allocate the memory address to a buffer addressing unit associated with a host interface, the memory address including a buffer memory identifier associated with a buffer memory block and a buffer memory address associated with the buffer memory block, and update a request count associated with the buffer memory block by incrementing a reference counter associated with the buffer memory block.

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